Files
avo/internal/gen/asmtest.go

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package gen
import (
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"fmt"
"math"
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"strconv"
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"strings"
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"sources.truenas.cloud/code/avo/internal/inst"
"sources.truenas.cloud/code/avo/internal/prnt"
"sources.truenas.cloud/code/avo/printer"
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)
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type asmtest struct {
cfg printer.Config
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sym string // reference to the test function symbol
rel8 string // label to be used for near jumps
rel32 string // label for far jumps
prnt.Generator
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}
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// NewAsmTest prints one massive assembly function containing a line for every
// instruction form in the database. The intention is to pass this to the Go
// assembler and confirm there are no errors, thus helping to ensure our
// database is compatible.
func NewAsmTest(cfg printer.Config) Interface {
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return &asmtest{cfg: cfg}
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}
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func (a *asmtest) Generate(is []inst.Instruction) ([]byte, error) {
a.Printf("// %s\n\n", a.cfg.GeneratedWarning())
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a.sym = "\u00b7loadertest(SB)"
a.Printf("TEXT %s, 0, $0\n", a.sym)
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// Define a label for far jumps.
a.Printf("rel32:\n")
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a.rel32 = "rel32"
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for _, i := range is {
a.Printf("\t// %s %s\n", i.Opcode, i.Summary)
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if skip, msg := a.skip(i.Opcode); skip {
a.Printf("\t// SKIP: %s\n", msg)
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continue
}
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if i.Opcode[0] == 'J' {
label := fmt.Sprintf("rel8_%s", strings.ToLower(i.Opcode))
a.Printf("%s:\n", label)
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a.rel8 = label
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}
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for _, f := range i.Forms {
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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as, err := a.args(i.Opcode, f.Operands)
if err != nil {
return nil, fmt.Errorf("tests for %s: %w", i.Opcode, err)
}
for _, suffixes := range f.SupportedSuffixes() {
opcode := i.Opcode
if len(suffixes) > 0 {
opcode += "." + suffixes.String()
}
a.Printf("\t%s\t%s\n", opcode, strings.Join(as, ", "))
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}
}
a.Printf("\n")
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}
a.Printf("\tRET\n")
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return a.Result()
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}
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func (a asmtest) skip(opcode string) (bool, string) {
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prefixes := map[string]string{
"PUSH": "PUSH can produce 'unbalanced PUSH/POP' assembler error",
"POP": "POP can produce 'unbalanced PUSH/POP' assembler error",
}
for p, m := range prefixes {
if strings.HasPrefix(opcode, p) {
return true, m
}
}
return false, ""
}
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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func (a asmtest) args(opcode string, ops []inst.Operand) ([]string, error) {
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// Special case for CALL, since it needs a different type of rel32 argument than others.
if opcode == "CALL" {
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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return []string{a.sym}, nil
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}
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as := make([]string, len(ops))
for i, op := range ops {
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a := a.arg(op.Type, i)
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if a == "" {
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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return nil, fmt.Errorf("unsupported operand type %q", op.Type)
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}
as[i] = a
}
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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return as, nil
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}
// arg generates an argument for an operand of the given type.
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func (a asmtest) arg(t string, i int) string {
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m := map[string]string{
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"1": "$1", // <xs:enumeration value="1" />
"3": "$3", // <xs:enumeration value="3" />
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"imm2u": "$3",
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// <xs:enumeration value="imm4" />
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"imm8": fmt.Sprintf("$%d", math.MaxInt8), // <xs:enumeration value="imm8" />
"imm16": fmt.Sprintf("$%d", math.MaxInt16), // <xs:enumeration value="imm16" />
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"imm32": fmt.Sprintf("$%d", math.MaxInt32), // <xs:enumeration value="imm32" />
"imm64": fmt.Sprintf("$%d", math.MaxInt64), // <xs:enumeration value="imm64" />
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"al": "AL", // <xs:enumeration value="al" />
"cl": "CL", // <xs:enumeration value="cl" />
"r8": "CH", // <xs:enumeration value="r8" />
"ax": "AX", // <xs:enumeration value="ax" />
"r16": "SI", // <xs:enumeration value="r16" />
"eax": "AX", // <xs:enumeration value="eax" />
"r32": "DX", // <xs:enumeration value="r32" />
"rax": "AX", // <xs:enumeration value="rax" />
"r64": "R15", // <xs:enumeration value="r64" />
"mm": "M5", // <xs:enumeration value="mm" />
"xmm0": "X0", // <xs:enumeration value="xmm0" />
"xmm": "X" + strconv.Itoa(7+i), // <xs:enumeration value="xmm" />
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// <xs:enumeration value="xmm{k}" />
// <xs:enumeration value="xmm{k}{z}" />
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"ymm": "Y" + strconv.Itoa(3+i), // <xs:enumeration value="ymm" />
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// <xs:enumeration value="ymm{k}" />
// <xs:enumeration value="ymm{k}{z}" />
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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"zmm": "Z" + strconv.Itoa(16+i), // <xs:enumeration value="zmm" />
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// <xs:enumeration value="zmm{k}" />
// <xs:enumeration value="zmm{k}{z}" />
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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"k": "K" + strconv.Itoa(1+i), // <xs:enumeration value="k" />
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// <xs:enumeration value="k{k}" />
// <xs:enumeration value="moffs32" />
// <xs:enumeration value="moffs64" />
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"m": "0(AX)(CX*2)", // <xs:enumeration value="m" />
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"m8": "8(AX)(CX*2)", // <xs:enumeration value="m8" />
"m16": "16(AX)(CX*2)", // <xs:enumeration value="m16" />
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// <xs:enumeration value="m16{k}{z}" />
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"m32": "32(AX)(CX*2)", // <xs:enumeration value="m32" />
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// <xs:enumeration value="m32{k}" />
// <xs:enumeration value="m32{k}{z}" />
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"m64": "64(AX)(CX*2)", // <xs:enumeration value="m64" />
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// <xs:enumeration value="m64{k}" />
// <xs:enumeration value="m64{k}{z}" />
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"m128": "128(AX)(CX*2)", // <xs:enumeration value="m128" />
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// <xs:enumeration value="m128{k}{z}" />
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"m256": "256(AX)(CX*2)", // <xs:enumeration value="m256" />
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// <xs:enumeration value="m256{k}{z}" />
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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"m512": "512(AX)(CX*2)", // <xs:enumeration value="m512" />
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// <xs:enumeration value="m512{k}{z}" />
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"vm32x": "32(X14*8)", // <xs:enumeration value="vm32x" />
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// <xs:enumeration value="vm32x{k}" />
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"vm64x": "64(X14*8)", // <xs:enumeration value="vm64x" />
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// <xs:enumeration value="vm64x{k}" />
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"vm32y": "32(Y13*8)", // <xs:enumeration value="vm32y" />
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// <xs:enumeration value="vm32y{k}" />
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"vm64y": "64(Y13*8)", // <xs:enumeration value="vm64y" />
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// <xs:enumeration value="vm64y{k}" />
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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"vm32z": "32(Z13*8)", // <xs:enumeration value="vm32z" />
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// <xs:enumeration value="vm32z{k}" />
all: AVX-512 (#217) Extends avo to support most AVX-512 instruction sets. The instruction type is extended to support suffixes. The K family of opmask registers is added to the register package, and the operand package is updated to support the new operand types. Move instruction deduction in `Load` and `Store` is extended to support KMOV* and VMOV* forms. Internal code generation packages were overhauled. Instruction database loading required various messy changes to account for the additional complexities of the AVX-512 instruction sets. The internal/api package was added to introduce a separation between instruction forms in the database, and the functions avo provides to create them. This was required since with instruction suffixes there is no longer a one-to-one mapping between instruction constructors and opcodes. AVX-512 bloated generated source code size substantially, initially increasing compilation and CI test times to an unacceptable level. Two changes were made to address this: 1. Instruction constructors in the `x86` package moved to an optab-based approach. This compiles substantially faster than the verbose code generation we had before. 2. The most verbose code-generated tests are moved under build tags and limited to a stress test mode. Stress test builds are run on schedule but not in regular CI. An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and test the new functionality. Updates #20 #163 #229 Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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"vm64z": "64(Z13*8)", // <xs:enumeration value="vm64z" />
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// <xs:enumeration value="vm64z{k}" />
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"rel8": a.rel8, // <xs:enumeration value="rel8" />
"rel32": a.rel32, // <xs:enumeration value="rel32" />
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// <xs:enumeration value="{er}" />
// <xs:enumeration value="{sae}" />
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// Appear unused:
"r8l": "????", // <xs:enumeration value="r8l" />
"r16l": "????", // <xs:enumeration value="r16l" />
"r32l": "????", // <xs:enumeration value="r32l" />
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}
return m[t]
}