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36e917b76871ff580f5ba8056dc3c54bcd7eaaec
avo/tests/alloc/masks/masks.s

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reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
// Code generated by command: go run asm.go -out masks.s -stubs stub.go. DO NOT EDIT.
#include "textflag.h"
// func Masks() (uint16, uint64)
pass: ensure frame pointer register is saved (#174) Currently `avo` uses `BP` as a standard general-purpose register. However, `BP` is used for the frame pointer and should be callee-save. Under some circumstances, the Go assembler will do this automatically, but not always. At the moment `avo` can produce code that clobbers the `BP` register. Since Go 1.16 this code will also fail a new `go vet` check. This PR provides a (currently sub-optimal) fix for the issue. It introduces an `EnsureBasePointerCalleeSaved` pass which will check if the base pointer is written to by a function, and if so will artificially ensure that the function has a non-zero frame size. This will trigger the Go assembler to automatically save and restore the BP register. In addition, we update the `asmdecl` tool to `asmvet`, which includes the `framepointer` vet check. Updates #156
2021-04-18 18:37:56 -07:00
TEXT ·Masks(SB), NOSPLIT, $8-16
reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
MOVQ $0x0001002a, AX
MOVQ $0x0002002a, CX
MOVQ $0x0003002a, DX
MOVQ $0x0004002a, BX
pass: de-prioritize base pointer in register allocation (#184) Updates #156
2021-04-18 19:22:09 -07:00
MOVQ $0x0005002a, SI
MOVQ $0x0006002a, DI
MOVQ $0x0007002a, R8
MOVQ $0x0008002a, R9
MOVQ $0x0009002a, R10
MOVQ $0x000a002a, R11
MOVQ $0x000b002a, R12
MOVQ $0x000c002a, R13
MOVQ $0x000d002a, R14
MOVQ $0x000e002a, R15
MOVQ $0x000f002a, BP
reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
MOVW $0x0001, AX
MOVW $0x0002, CX
MOVW $0x0003, DX
MOVW $0x0004, BX
pass: de-prioritize base pointer in register allocation (#184) Updates #156
2021-04-18 19:22:09 -07:00
MOVW $0x0005, SI
MOVW $0x0006, DI
MOVW $0x0007, R8
MOVW $0x0008, R9
MOVW $0x0009, R10
MOVW $0x000a, R11
MOVW $0x000b, R12
MOVW $0x000c, R13
MOVW $0x000d, R14
MOVW $0x000e, R15
MOVW $0x000f, BP
reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
ADDW CX, AX
ADDW DX, AX
ADDW BX, AX
ADDW SI, AX
ADDW DI, AX
ADDW R8, AX
ADDW R9, AX
ADDW R10, AX
ADDW R11, AX
ADDW R12, AX
ADDW R13, AX
ADDW R14, AX
ADDW R15, AX
pass: de-prioritize base pointer in register allocation (#184) Updates #156
2021-04-18 19:22:09 -07:00
ADDW BP, AX
reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
MOVW AX, ret+0(FP)
MOVW $0x0000, AX
MOVW $0x0000, CX
MOVW $0x0000, DX
MOVW $0x0000, BX
MOVW $0x0000, SI
MOVW $0x0000, DI
MOVW $0x0000, R8
MOVW $0x0000, R9
MOVW $0x0000, R10
MOVW $0x0000, R11
MOVW $0x0000, R12
MOVW $0x0000, R13
MOVW $0x0000, R14
MOVW $0x0000, R15
pass: de-prioritize base pointer in register allocation (#184) Updates #156
2021-04-18 19:22:09 -07:00
MOVW $0x0000, BP
reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
ADDQ CX, AX
ADDQ DX, AX
ADDQ BX, AX
ADDQ SI, AX
ADDQ DI, AX
ADDQ R8, AX
ADDQ R9, AX
ADDQ R10, AX
ADDQ R11, AX
ADDQ R12, AX
ADDQ R13, AX
ADDQ R14, AX
ADDQ R15, AX
pass: de-prioritize base pointer in register allocation (#184) Updates #156
2021-04-18 19:22:09 -07:00
ADDQ BP, AX
reg,pass: refactor allocation of aliased registers (#121) Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
2020-01-22 22:50:40 -08:00
SHRQ $0x10, AX
MOVQ AX, ret1+8(FP)
RET
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