109 lines
2.7 KiB
Go
109 lines
2.7 KiB
Go
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package gen
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import (
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"strings"
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"github.com/mmcloughlin/avo/internal/inst"
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)
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type ctorstest struct {
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cfg Config
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printer
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}
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func NewCtorsTest(cfg Config) Interface {
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return GoFmt(&ctorstest{cfg: cfg})
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}
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func (c *ctorstest) Generate(is []inst.Instruction) ([]byte, error) {
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c.Printf("// %s\n\n", c.cfg.GeneratedWarning())
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c.Printf("package x86\n\n")
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c.Printf("import (\n")
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c.Printf("\t\"testing\"\n")
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c.Printf("\t\"math\"\n")
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c.Printf("\t\"%s/reg\"\n", pkg)
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c.Printf("\t\"%s/operand\"\n", pkg)
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c.Printf(")\n\n")
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for _, i := range is {
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c.instruction(i)
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}
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return c.Result()
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}
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func (c *ctorstest) instruction(i inst.Instruction) {
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c.Printf("func Test%sValidForms(t *testing.T) {", i.Opcode)
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for _, f := range i.Forms {
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name := strings.Join(f.Signature(), "_")
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c.Printf("t.Run(\"form=%s\", func(t *testing.T) {\n", name)
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for _, args := range validFormArgs(f) {
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c.Printf("if _, err := %s(%s)", i.Opcode, strings.Join(args, ", "))
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c.Printf("; err != nil { t.Fatal(err) }\n")
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}
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c.Printf("})\n")
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}
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c.Printf("}\n\n")
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}
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func validFormArgs(f inst.Form) [][]string {
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n := len(f.Operands)
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args := make([][]string, n)
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for i, op := range f.Operands {
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valid, ok := validArgs[op.Type]
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if !ok {
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panic("missing operands for type " + op.Type)
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}
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args[i] = valid
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}
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return cross(args)
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}
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var validArgs = map[string][]string{
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// Immediates
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"1": {"operand.Imm(1)"},
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"3": {"operand.Imm(3)"},
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"imm2u": {"operand.Imm(3)"},
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"imm8": {"operand.Imm(math.MaxInt8)"},
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"imm16": {"operand.Imm(math.MaxInt16)"},
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"imm32": {"operand.Imm(math.MaxInt32)"},
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"imm64": {"operand.Imm(math.MaxInt64)"},
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// Registers
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"al": {"reg.AL"},
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"cl": {"reg.CL"},
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"ax": {"reg.AX"},
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"eax": {"reg.EAX"},
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"rax": {"reg.RAX"},
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"r8": {"reg.CH"},
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"r16": {"reg.R9W"},
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"r32": {"reg.R10L"},
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"r64": {"reg.R11"},
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"xmm0": {"reg.X0"},
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"xmm": {"reg.X7"},
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"ymm": {"reg.Y15"},
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// Memory
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"m": {"operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}"},
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"m8": {"operand.Mem{Base: reg.BL, Index: reg.CH, Scale: 1}"},
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"m16": {"operand.Mem{Base: reg.BX, Index: reg.CX, Scale: 2}"},
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"m32": {"operand.Mem{Base: reg.EBX, Index: reg.ECX, Scale: 4}"},
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"m64": {"operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"},
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"m128": {"operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"},
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"m256": {"operand.Mem{Base: reg.RBX, Index: reg.RCX, Scale: 8}"},
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// Vector memory
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"vm32x": {"operand.Mem{Base: reg.R13, Index: reg.X4, Scale: 1}"},
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"vm64x": {"operand.Mem{Base: reg.R13, Index: reg.X8, Scale: 1}"},
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"vm32y": {"operand.Mem{Base: reg.R13, Index: reg.Y4, Scale: 1}"},
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"vm64y": {"operand.Mem{Base: reg.R13, Index: reg.Y8, Scale: 1}"},
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// Relative
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"rel8": {"operand.Rel(math.MaxInt8)"},
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"rel32": {"operand.Rel(math.MaxInt32)", "operand.LabelRef(\"lbl\")"},
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}
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