pass: first attempt at register allocation

This commit is contained in:
Michael McLoughlin
2018-12-05 00:05:57 -08:00
parent 9376a230cf
commit 022cbb7792
9 changed files with 394 additions and 24 deletions

View File

@@ -23,14 +23,43 @@ func TestSpecBytes(t *testing.T) {
}
}
func TestVirtualPhysicalHaveDifferentIDs(t *testing.T) {
// Confirm that ID() returns different results even when virtual and physical IDs are the same.
var v Virtual = virtual{id: 42}
var p Physical = register{id: 42}
if uint16(v.VirtualID()) != uint16(p.PhysicalID()) {
t.Fatal("test assumption violated: VirtualID and PhysicalID should agree")
func TestToVirtual(t *testing.T) {
v := GeneralPurpose.Virtual(42, B32)
if ToVirtual(v) != v {
t.Errorf("ToVirtual(v) != v for virtual register")
}
if v.ID() == p.ID() {
t.Errorf("virtual and physical IDs should be different")
if ToVirtual(ECX) != nil {
t.Errorf("ToVirtual should be nil for physical registers")
}
}
func TestToPhysical(t *testing.T) {
v := GeneralPurpose.Virtual(42, B32)
if ToPhysical(v) != nil {
t.Errorf("ToPhysical should be nil for virtual registers")
}
if ToPhysical(ECX) != ECX {
t.Errorf("ToPhysical(p) != p for physical register")
}
}
func TestAreConflicting(t *testing.T) {
cases := []struct {
X, Y Physical
Expect bool
}{
{ECX, X3, false},
{AL, AH, false},
{AL, AX, true},
{AL, BX, false},
{X3, Y4, false},
{X3, Y3, true},
{Y3, Z4, false},
{Y3, Z3, true},
}
for _, c := range cases {
if AreConflicting(c.X, c.Y) != c.Expect {
t.Errorf("AreConflicting(%s, %s) != %v", c.X, c.Y, c.Expect)
}
}
}

View File

@@ -1,7 +1,7 @@
package reg
// Set is a set of registers.
type Set map[ID]Register
type Set map[Register]bool
// NewEmptySet builds an empty register set.
func NewEmptySet() Set {
@@ -20,7 +20,7 @@ func NewSetFromSlice(rs []Register) Set {
// Clone returns a copy of s.
func (s Set) Clone() Set {
c := NewEmptySet()
for _, r := range s {
for r := range s {
c.Add(r)
}
return c
@@ -28,17 +28,17 @@ func (s Set) Clone() Set {
// Add r to s.
func (s Set) Add(r Register) {
s[r.ID()] = r
s[r] = true
}
// Discard removes r from s, if present.
func (s Set) Discard(r Register) {
delete(s, r.ID())
delete(s, r)
}
// Update adds every register in t to s.
func (s Set) Update(t Set) {
for _, r := range t {
for r := range t {
s.Add(r)
}
}
@@ -52,7 +52,7 @@ func (s Set) Difference(t Set) Set {
// DifferenceUpdate removes every element of t from s.
func (s Set) DifferenceUpdate(t Set) {
for _, r := range t {
for r := range t {
s.Discard(r)
}
}
@@ -62,10 +62,21 @@ func (s Set) Equals(t Set) bool {
if len(s) != len(t) {
return false
}
for _, r := range s {
if _, found := t[r.ID()]; !found {
for r := range s {
if _, found := t[r]; !found {
return false
}
}
return true
}
// OfKind returns the set of elements of s with kind k.
func (s Set) OfKind(k Kind) Set {
t := NewEmptySet()
for r := range s {
if r.Kind() == k {
t.Add(r)
}
}
return t
}

View File

@@ -2,11 +2,40 @@ package reg
import "testing"
func TestFamilyRegisterSets(t *testing.T) {
fs := []*Family{GeneralPurpose, SIMD}
for _, f := range fs {
if len(f.Set()) != len(f.Registers()) {
t.Fatal("family set and list should have same size")
}
func TestSetRegisterIdentity(t *testing.T) {
rs := []Register{
NewVirtual(42, GP, B32),
NewVirtual(43, GP, B32),
NewVirtual(42, SSEAVX, B32),
NewVirtual(42, GP, B64),
AL, AH, CL,
AX, R13W,
EDX, R9L,
RCX, R14,
X1, X7,
Y4, Y9,
Z13, Z31,
}
s := NewEmptySet()
for _, r := range rs {
s.Add(r)
s.Add(r)
}
if len(s) != len(rs) {
t.Fatalf("expected set to have same size as slice: got %d expect %d", len(s), len(rs))
}
}
func TestSetFamilyRegisters(t *testing.T) {
fs := []*Family{GeneralPurpose, SIMD}
s := NewEmptySet()
expect := 0
for _, f := range fs {
s.Update(f.Set())
s.Add(f.Virtual(42, B64))
expect += len(f.Registers()) + 1
}
if len(s) != expect {
t.Fatalf("set size mismatch: %d expected %d", len(s), expect)
}
}

View File

@@ -1,6 +1,7 @@
package reg
import (
"errors"
"fmt"
)
@@ -63,7 +64,7 @@ type private interface {
}
type (
ID uint32
ID uint64
VID uint16
PID uint16
)
@@ -81,6 +82,14 @@ type Virtual interface {
Register
}
// ToVirtual converts r to Virtual if possible, otherwise returns nil.
func ToVirtual(r Register) Virtual {
if v, ok := r.(Virtual); ok {
return v
}
return nil
}
type virtual struct {
id VID
kind Kind
@@ -99,7 +108,7 @@ func (v virtual) VirtualID() VID { return v.id }
func (v virtual) Kind() Kind { return v.kind }
func (v virtual) ID() ID {
return (ID(1) << 31) | ID(v.VirtualID())
return (ID(1) << 63) | (ID(v.Size) << 24) | (ID(v.kind) << 16) | ID(v.VirtualID())
}
func (v virtual) Asm() string {
@@ -115,6 +124,14 @@ type Physical interface {
Register
}
// ToPhysical converts r to Physical if possible, otherwise returns nil.
func ToPhysical(r Register) Physical {
if p, ok := r.(Physical); ok {
return p
}
return nil
}
type register struct {
id PID
kind Kind
@@ -155,3 +172,34 @@ func (s Spec) Bytes() uint {
x := uint(s)
return (x >> 1) + (x & 1)
}
// AreConflicting returns whether registers conflict with each other.
func AreConflicting(x, y Physical) bool {
return x.Kind() == y.Kind() && x.PhysicalID() == y.PhysicalID() && (x.Mask()&y.Mask()) != 0
}
// Allocation records a register allocation.
type Allocation map[Register]Physical
func NewEmptyAllocation() Allocation {
return Allocation{}
}
// Merge allocations from b into a. Errors if there is disagreement on a common
// register.
func (a Allocation) Merge(b Allocation) error {
for r, p := range b {
if alt, found := a[r]; found && alt != p {
return errors.New("disagreement on overlapping register")
}
a[r] = p
}
return nil
}
func (a Allocation) LookupDefault(r Register) Register {
if p, found := a[r]; found {
return p
}
return r
}

View File

@@ -8,6 +8,23 @@ const (
Mask
)
var Families = []*Family{
GeneralPurpose,
SIMD,
}
var familiesByKind = map[Kind]*Family{}
func init() {
for _, f := range Families {
familiesByKind[f.Kind] = f
}
}
func FamilyOfKind(k Kind) *Family {
return familiesByKind[k]
}
// General purpose registers.
var (
GeneralPurpose = &Family{Kind: GP}