From 05ed388d0f330946c08f331cd897f32d63d50ec5 Mon Sep 17 00:00:00 2001 From: Michael McLoughlin Date: Tue, 10 Jan 2023 18:55:12 -0800 Subject: [PATCH] all: BITALG instructions (#362) Adds the AVX-512 Bit Algorithms instruction set. These new instructions are added via the `opcodesextra` mechanism #345, since they're missing from the opcodes database. Contributed by @vsivsi. Extracted from #234 with simplifications for AVX-512 form expansion. Co-authored-by: Vaughn Iverson --- build/zinstructions.go | 191 +++++++++++ build/zinstructions_test.go | 5 + internal/inst/ztable.go | 456 ++++++++++++++++++++++++++ internal/opcodesextra/bitalg.go | 188 +++++++++++ internal/opcodesextra/instructions.go | 1 + x86/zctors.go | 88 +++++ x86/zctors_test.go | 159 +++++++++ x86/zoptab.go | 379 ++++++++++++--------- 8 files changed, 1308 insertions(+), 159 deletions(-) create mode 100644 internal/opcodesextra/bitalg.go diff --git a/build/zinstructions.go b/build/zinstructions.go index 4c50e91..6e8261a 100644 --- a/build/zinstructions.go +++ b/build/zinstructions.go @@ -69244,6 +69244,80 @@ func (c *Context) VPMULUDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { // Operates on the global context. func VPMULUDQ_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPMULUDQ_Z(mxyz, xyz, k, xyz1) } +// VPOPCNTB: Packed Population Count for Byte Integers. +// +// Forms: +// +// VPOPCNTB m128 k xmm +// VPOPCNTB m128 xmm +// VPOPCNTB m256 k ymm +// VPOPCNTB m256 ymm +// VPOPCNTB xmm k xmm +// VPOPCNTB xmm xmm +// VPOPCNTB ymm k ymm +// VPOPCNTB ymm ymm +// VPOPCNTB m512 k zmm +// VPOPCNTB m512 zmm +// VPOPCNTB zmm k zmm +// VPOPCNTB zmm zmm +// +// Construct and append a VPOPCNTB instruction to the active function. +func (c *Context) VPOPCNTB(ops ...operand.Op) { + c.addinstruction(x86.VPOPCNTB(ops...)) +} + +// VPOPCNTB: Packed Population Count for Byte Integers. +// +// Forms: +// +// VPOPCNTB m128 k xmm +// VPOPCNTB m128 xmm +// VPOPCNTB m256 k ymm +// VPOPCNTB m256 ymm +// VPOPCNTB xmm k xmm +// VPOPCNTB xmm xmm +// VPOPCNTB ymm k ymm +// VPOPCNTB ymm ymm +// VPOPCNTB m512 k zmm +// VPOPCNTB m512 zmm +// VPOPCNTB zmm k zmm +// VPOPCNTB zmm zmm +// +// Construct and append a VPOPCNTB instruction to the active function. +// Operates on the global context. +func VPOPCNTB(ops ...operand.Op) { ctx.VPOPCNTB(ops...) } + +// VPOPCNTB_Z: Packed Population Count for Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPOPCNTB.Z m128 k xmm +// VPOPCNTB.Z m256 k ymm +// VPOPCNTB.Z xmm k xmm +// VPOPCNTB.Z ymm k ymm +// VPOPCNTB.Z m512 k zmm +// VPOPCNTB.Z zmm k zmm +// +// Construct and append a VPOPCNTB.Z instruction to the active function. +func (c *Context) VPOPCNTB_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPOPCNTB_Z(mxyz, k, xyz)) +} + +// VPOPCNTB_Z: Packed Population Count for Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPOPCNTB.Z m128 k xmm +// VPOPCNTB.Z m256 k ymm +// VPOPCNTB.Z xmm k xmm +// VPOPCNTB.Z ymm k ymm +// VPOPCNTB.Z m512 k zmm +// VPOPCNTB.Z zmm k zmm +// +// Construct and append a VPOPCNTB.Z instruction to the active function. +// Operates on the global context. +func VPOPCNTB_Z(mxyz, k, xyz operand.Op) { ctx.VPOPCNTB_Z(mxyz, k, xyz) } + // VPOPCNTD: Packed Population Count for Doubleword Integers. // // Forms: @@ -69504,6 +69578,80 @@ func (c *Context) VPOPCNTQ_Z(mxyz, k, xyz operand.Op) { // Operates on the global context. func VPOPCNTQ_Z(mxyz, k, xyz operand.Op) { ctx.VPOPCNTQ_Z(mxyz, k, xyz) } +// VPOPCNTW: Packed Population Count for Word Integers. +// +// Forms: +// +// VPOPCNTW m128 k xmm +// VPOPCNTW m128 xmm +// VPOPCNTW m256 k ymm +// VPOPCNTW m256 ymm +// VPOPCNTW xmm k xmm +// VPOPCNTW xmm xmm +// VPOPCNTW ymm k ymm +// VPOPCNTW ymm ymm +// VPOPCNTW m512 k zmm +// VPOPCNTW m512 zmm +// VPOPCNTW zmm k zmm +// VPOPCNTW zmm zmm +// +// Construct and append a VPOPCNTW instruction to the active function. +func (c *Context) VPOPCNTW(ops ...operand.Op) { + c.addinstruction(x86.VPOPCNTW(ops...)) +} + +// VPOPCNTW: Packed Population Count for Word Integers. +// +// Forms: +// +// VPOPCNTW m128 k xmm +// VPOPCNTW m128 xmm +// VPOPCNTW m256 k ymm +// VPOPCNTW m256 ymm +// VPOPCNTW xmm k xmm +// VPOPCNTW xmm xmm +// VPOPCNTW ymm k ymm +// VPOPCNTW ymm ymm +// VPOPCNTW m512 k zmm +// VPOPCNTW m512 zmm +// VPOPCNTW zmm k zmm +// VPOPCNTW zmm zmm +// +// Construct and append a VPOPCNTW instruction to the active function. +// Operates on the global context. +func VPOPCNTW(ops ...operand.Op) { ctx.VPOPCNTW(ops...) } + +// VPOPCNTW_Z: Packed Population Count for Word Integers (Zeroing Masking). +// +// Forms: +// +// VPOPCNTW.Z m128 k xmm +// VPOPCNTW.Z m256 k ymm +// VPOPCNTW.Z xmm k xmm +// VPOPCNTW.Z ymm k ymm +// VPOPCNTW.Z m512 k zmm +// VPOPCNTW.Z zmm k zmm +// +// Construct and append a VPOPCNTW.Z instruction to the active function. +func (c *Context) VPOPCNTW_Z(mxyz, k, xyz operand.Op) { + c.addinstruction(x86.VPOPCNTW_Z(mxyz, k, xyz)) +} + +// VPOPCNTW_Z: Packed Population Count for Word Integers (Zeroing Masking). +// +// Forms: +// +// VPOPCNTW.Z m128 k xmm +// VPOPCNTW.Z m256 k ymm +// VPOPCNTW.Z xmm k xmm +// VPOPCNTW.Z ymm k ymm +// VPOPCNTW.Z m512 k zmm +// VPOPCNTW.Z zmm k zmm +// +// Construct and append a VPOPCNTW.Z instruction to the active function. +// Operates on the global context. +func VPOPCNTW_Z(mxyz, k, xyz operand.Op) { ctx.VPOPCNTW_Z(mxyz, k, xyz) } + // VPOR: Packed Bitwise Logical OR. // // Forms: @@ -71005,6 +71153,49 @@ func (c *Context) VPSHUFB(ops ...operand.Op) { // Operates on the global context. func VPSHUFB(ops ...operand.Op) { ctx.VPSHUFB(ops...) } +// VPSHUFBITQMB: Shuffle Bits from Quadword Elements Using Byte Indexes into Mask. +// +// Forms: +// +// VPSHUFBITQMB m128 xmm k k +// VPSHUFBITQMB m128 xmm k +// VPSHUFBITQMB m256 ymm k k +// VPSHUFBITQMB m256 ymm k +// VPSHUFBITQMB xmm xmm k k +// VPSHUFBITQMB xmm xmm k +// VPSHUFBITQMB ymm ymm k k +// VPSHUFBITQMB ymm ymm k +// VPSHUFBITQMB zmm zmm k k +// VPSHUFBITQMB zmm zmm k +// VPSHUFBITQMB m512 zmm k k +// VPSHUFBITQMB m512 zmm k +// +// Construct and append a VPSHUFBITQMB instruction to the active function. +func (c *Context) VPSHUFBITQMB(ops ...operand.Op) { + c.addinstruction(x86.VPSHUFBITQMB(ops...)) +} + +// VPSHUFBITQMB: Shuffle Bits from Quadword Elements Using Byte Indexes into Mask. +// +// Forms: +// +// VPSHUFBITQMB m128 xmm k k +// VPSHUFBITQMB m128 xmm k +// VPSHUFBITQMB m256 ymm k k +// VPSHUFBITQMB m256 ymm k +// VPSHUFBITQMB xmm xmm k k +// VPSHUFBITQMB xmm xmm k +// VPSHUFBITQMB ymm ymm k k +// VPSHUFBITQMB ymm ymm k +// VPSHUFBITQMB zmm zmm k k +// VPSHUFBITQMB zmm zmm k +// VPSHUFBITQMB m512 zmm k k +// VPSHUFBITQMB m512 zmm k +// +// Construct and append a VPSHUFBITQMB instruction to the active function. +// Operates on the global context. +func VPSHUFBITQMB(ops ...operand.Op) { ctx.VPSHUFBITQMB(ops...) } + // VPSHUFB_Z: Packed Shuffle Bytes (Zeroing Masking). // // Forms: diff --git a/build/zinstructions_test.go b/build/zinstructions_test.go index c95de4f..e3c4469 100644 --- a/build/zinstructions_test.go +++ b/build/zinstructions_test.go @@ -2672,6 +2672,8 @@ func TestContextInstructions(t *testing.T) { ctx.VPMULUDQ_BCST(opm64, opxmm, opk, opxmm) ctx.VPMULUDQ_BCST_Z(opm64, opxmm, opk, opxmm) ctx.VPMULUDQ_Z(opm128, opxmm, opk, opxmm) + ctx.VPOPCNTB(opm128, opk, opxmm) + ctx.VPOPCNTB_Z(opm128, opk, opxmm) ctx.VPOPCNTD(opm128, opk, opxmm) ctx.VPOPCNTD_BCST(opm32, opk, opxmm) ctx.VPOPCNTD_BCST_Z(opm32, opk, opxmm) @@ -2680,6 +2682,8 @@ func TestContextInstructions(t *testing.T) { ctx.VPOPCNTQ_BCST(opm64, opk, opxmm) ctx.VPOPCNTQ_BCST_Z(opm64, opk, opxmm) ctx.VPOPCNTQ_Z(opm128, opk, opxmm) + ctx.VPOPCNTW(opm128, opk, opxmm) + ctx.VPOPCNTW_Z(opm128, opk, opxmm) ctx.VPOR(opm256, opymm, opymm) ctx.VPORD(opm128, opxmm, opk, opxmm) ctx.VPORD_BCST(opm32, opxmm, opk, opxmm) @@ -2727,6 +2731,7 @@ func TestContextInstructions(t *testing.T) { ctx.VPSCATTERQD(opxmm, opk, opvm64x) ctx.VPSCATTERQQ(opxmm, opk, opvm64x) ctx.VPSHUFB(opm256, opymm, opymm) + ctx.VPSHUFBITQMB(opm128, opxmm, opk, opk) ctx.VPSHUFB_Z(opm128, opxmm, opk, opxmm) ctx.VPSHUFD(opimm8, opm256, opymm) ctx.VPSHUFD_BCST(opimm8, opm32, opk, opxmm) diff --git a/internal/inst/ztable.go b/internal/inst/ztable.go index 974a27b..e50fccd 100644 --- a/internal/inst/ztable.go +++ b/internal/inst/ztable.go @@ -91515,6 +91515,174 @@ var Instructions = []Instruction{ }, }, }, + { + Opcode: "VPOPCNTB", + Summary: "Packed Population Count for Byte Integers", + Forms: []Form{ + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, { Opcode: "VPOPCNTD", Summary: "Packed Population Count for Doubleword Integers", @@ -92031,6 +92199,174 @@ var Instructions = []Instruction{ }, }, }, + { + Opcode: "VPOPCNTW", + Summary: "Packed Population Count for Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, { Opcode: "VPOR", Summary: "Packed Bitwise Logical OR", @@ -95304,6 +95640,126 @@ var Instructions = []Instruction{ }, }, }, + { + Opcode: "VPSHUFBITQMB", + Summary: "Shuffle Bits from Quadword Elements Using Byte Indexes into Mask", + Forms: []Form{ + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x2}, + }, + EncodingType: 0x4, + }, + }, + }, { Opcode: "VPSHUFD", Summary: "Shuffle Packed Doublewords", diff --git a/internal/opcodesextra/bitalg.go b/internal/opcodesextra/bitalg.go new file mode 100644 index 0000000..a64f1f0 --- /dev/null +++ b/internal/opcodesextra/bitalg.go @@ -0,0 +1,188 @@ +package opcodesextra + +import "github.com/mmcloughlin/avo/internal/inst" + +// bitalg is the AVX-512 Bit Algorithms instruction set. +var bitalg = []*inst.Instruction{ + // Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L3904-L3908 + // + // {as: AVPSHUFBITQMB, ytab: _yvpshufbitqmb, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16, 0x8F, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32, 0x8F, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64, 0x8F, + // }}, + // + { + Opcode: "VPSHUFBITQMB", + Summary: "Shuffle Bits from Quadword Elements Using Byte Indexes into Mask", + Forms: vpshufbitqmb, + }, + // Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L3736-L3740 + // + // {as: AVPOPCNTB, ytab: _yvexpandpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexZeroingEnabled, 0x54, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexZeroingEnabled, 0x54, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexZeroingEnabled, 0x54, + // }}, + // + { + Opcode: "VPOPCNTB", + Summary: "Packed Population Count for Byte Integers", + Forms: vpopcntb, + }, + // Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L3751-L3755 + // + // {as: AVPOPCNTW, ytab: _yvexpandpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW1, evexN16 | evexZeroingEnabled, 0x54, + // avxEscape | evex256 | evex66 | evex0F38 | evexW1, evexN32 | evexZeroingEnabled, 0x54, + // avxEscape | evex512 | evex66 | evex0F38 | evexW1, evexN64 | evexZeroingEnabled, 0x54, + // }}, + // + { + Opcode: "VPOPCNTW", + Summary: "Packed Population Count for Word Integers", + Forms: vpopcntb, + }, +} + +// VPSHUFBITQMB forms. +// +// See: https://www.felixcloutier.com/x86/vpshufbitqmb +// +// Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L827-L834 +// +// var _yvpshufbitqmb = []ytab{ +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{YxmEvex, YxrEvex, Yk}}, +// {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{YxmEvex, YxrEvex, Yknot0, Yk}}, +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{YymEvex, YyrEvex, Yk}}, +// {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{YymEvex, YyrEvex, Yknot0, Yk}}, +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{Yzm, Yzr, Yk}}, +// {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{Yzm, Yzr, Yknot0, Yk}}, +// } +var vpshufbitqmb = inst.Forms{ + // EVEX.128.66.0F38.W0 8F /r VPSHUFBITQMB k1{k2}, xmm2, xmm3/m128 + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "m128", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k{k}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k{k}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + // EVEX.256.66.0F38.W0 8F /r VPSHUFBITQMB k1{k2}, ymm2, ymm3/m256 + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "m256", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k{k}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k{k}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + // EVEX.512.66.0F38.W0 8F /r VPSHUFBITQMB k1{k2}, zmm2, zmm3/m512 + { + ISA: []string{"AVX512BITALG"}, + Operands: []inst.Operand{ + {Type: "m512", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k{k}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k{k}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, +} + +// VPOPCNTB and VPOPCNTW forms. +// +// See: https://www.felixcloutier.com/x86/vpopcnt +// +// Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L376-L383 +// +// var _yvexpandpd = []ytab{ +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{YxmEvex, YxrEvex}}, +// {zcase: Zevex_rm_k_r, zoffset: 3, args: argList{YxmEvex, Yknot0, YxrEvex}}, +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{YymEvex, YyrEvex}}, +// {zcase: Zevex_rm_k_r, zoffset: 3, args: argList{YymEvex, Yknot0, YyrEvex}}, +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{Yzm, Yzr}}, +// {zcase: Zevex_rm_k_r, zoffset: 3, args: argList{Yzm, Yknot0, Yzr}}, +// } +var vpopcntb = inst.Forms{ + // EVEX.128.66.0F38.W0 54 /r VPOPCNTB xmm1{k1}{z}, xmm2/m128 + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "m128", Action: inst.R}, + {Type: "xmm{k}{z}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "xmm", Action: inst.R}, + {Type: "xmm{k}{z}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + // EVEX.256.66.0F38.W0 54 /r VPOPCNTB ymm1{k1}{z}, ymm2/m256 + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "m256", Action: inst.R}, + {Type: "ymm{k}{z}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512BITALG", "AVX512VL"}, + Operands: []inst.Operand{ + {Type: "ymm", Action: inst.R}, + {Type: "ymm{k}{z}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + // EVEX.512.66.0F38.W0 54 /r VPOPCNTB zmm1{k1}{z}, zmm2/m512 + { + ISA: []string{"AVX512BITALG"}, + Operands: []inst.Operand{ + {Type: "m512", Action: inst.R}, + {Type: "zmm{k}{z}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512BITALG"}, + Operands: []inst.Operand{ + {Type: "zmm", Action: inst.R}, + {Type: "zmm{k}{z}", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, +} diff --git a/internal/opcodesextra/instructions.go b/internal/opcodesextra/instructions.go index c49aeff..c88e15d 100644 --- a/internal/opcodesextra/instructions.go +++ b/internal/opcodesextra/instructions.go @@ -11,6 +11,7 @@ var sets = [][]*inst.Instruction{ vnni, vpclmulqdq, vpopcntdq, + bitalg, } // Instructions returns a list of extras to add to the instructions database. diff --git a/x86/zctors.go b/x86/zctors.go index a74c0c2..f4d6992 100644 --- a/x86/zctors.go +++ b/x86/zctors.go @@ -30694,6 +30694,40 @@ func VPMULUDQ_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { return build(opcVPMULUDQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) } +// VPOPCNTB: Packed Population Count for Byte Integers. +// +// Forms: +// +// VPOPCNTB m128 k xmm +// VPOPCNTB m128 xmm +// VPOPCNTB m256 k ymm +// VPOPCNTB m256 ymm +// VPOPCNTB xmm k xmm +// VPOPCNTB xmm xmm +// VPOPCNTB ymm k ymm +// VPOPCNTB ymm ymm +// VPOPCNTB m512 k zmm +// VPOPCNTB m512 zmm +// VPOPCNTB zmm k zmm +// VPOPCNTB zmm zmm +func VPOPCNTB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTB.Forms(), sffxs{}, ops) +} + +// VPOPCNTB_Z: Packed Population Count for Byte Integers (Zeroing Masking). +// +// Forms: +// +// VPOPCNTB.Z m128 k xmm +// VPOPCNTB.Z m256 k ymm +// VPOPCNTB.Z xmm k xmm +// VPOPCNTB.Z ymm k ymm +// VPOPCNTB.Z m512 k zmm +// VPOPCNTB.Z zmm k zmm +func VPOPCNTB_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTB.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + // VPOPCNTD: Packed Population Count for Doubleword Integers. // // Forms: @@ -30812,6 +30846,40 @@ func VPOPCNTQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { return build(opcVPOPCNTQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } +// VPOPCNTW: Packed Population Count for Word Integers. +// +// Forms: +// +// VPOPCNTW m128 k xmm +// VPOPCNTW m128 xmm +// VPOPCNTW m256 k ymm +// VPOPCNTW m256 ymm +// VPOPCNTW xmm k xmm +// VPOPCNTW xmm xmm +// VPOPCNTW ymm k ymm +// VPOPCNTW ymm ymm +// VPOPCNTW m512 k zmm +// VPOPCNTW m512 zmm +// VPOPCNTW zmm k zmm +// VPOPCNTW zmm zmm +func VPOPCNTW(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTW.Forms(), sffxs{}, ops) +} + +// VPOPCNTW_Z: Packed Population Count for Word Integers (Zeroing Masking). +// +// Forms: +// +// VPOPCNTW.Z m128 k xmm +// VPOPCNTW.Z m256 k ymm +// VPOPCNTW.Z xmm k xmm +// VPOPCNTW.Z ymm k ymm +// VPOPCNTW.Z m512 k zmm +// VPOPCNTW.Z zmm k zmm +func VPOPCNTW_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { + return build(opcVPOPCNTW.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) +} + // VPOR: Packed Bitwise Logical OR. // // Forms: @@ -31492,6 +31560,26 @@ func VPSHUFB(ops ...operand.Op) (*intrep.Instruction, error) { return build(opcVPSHUFB.Forms(), sffxs{}, ops) } +// VPSHUFBITQMB: Shuffle Bits from Quadword Elements Using Byte Indexes into Mask. +// +// Forms: +// +// VPSHUFBITQMB m128 xmm k k +// VPSHUFBITQMB m128 xmm k +// VPSHUFBITQMB m256 ymm k k +// VPSHUFBITQMB m256 ymm k +// VPSHUFBITQMB xmm xmm k k +// VPSHUFBITQMB xmm xmm k +// VPSHUFBITQMB ymm ymm k k +// VPSHUFBITQMB ymm ymm k +// VPSHUFBITQMB zmm zmm k k +// VPSHUFBITQMB zmm zmm k +// VPSHUFBITQMB m512 zmm k k +// VPSHUFBITQMB m512 zmm k +func VPSHUFBITQMB(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPSHUFBITQMB.Forms(), sffxs{}, ops) +} + // VPSHUFB_Z: Packed Shuffle Bytes (Zeroing Masking). // // Forms: diff --git a/x86/zctors_test.go b/x86/zctors_test.go index 620b007..8995223 100644 --- a/x86/zctors_test.go +++ b/x86/zctors_test.go @@ -37178,6 +37178,66 @@ func TestVPMULUDQ_ZValidFormsNoError(t *testing.T) { } } +func TestVPOPCNTBValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTB(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTB_ZValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTB_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTB_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + func TestVPOPCNTDValidFormsNoError(t *testing.T) { if _, err := VPOPCNTD(opm128, opk, opxmm); err != nil { t.Fatal(err) @@ -37364,6 +37424,66 @@ func TestVPOPCNTQ_ZValidFormsNoError(t *testing.T) { } } +func TestVPOPCNTWValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTW(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opm128, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opm256, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opm512, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW(opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPOPCNTW_ZValidFormsNoError(t *testing.T) { + if _, err := VPOPCNTW_Z(opm128, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW_Z(opm256, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW_Z(opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW_Z(opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW_Z(opm512, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPOPCNTW_Z(opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + func TestVPORValidFormsNoError(t *testing.T) { if _, err := VPOR(opm256, opymm, opymm); err != nil { t.Fatal(err) @@ -38417,6 +38537,45 @@ func TestVPSHUFBValidFormsNoError(t *testing.T) { } } +func TestVPSHUFBITQMBValidFormsNoError(t *testing.T) { + if _, err := VPSHUFBITQMB(opm128, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opm128, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opm256, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opm256, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opxmm, opxmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opxmm, opxmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opymm, opymm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opymm, opymm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opzmm, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opzmm, opzmm, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opm512, opzmm, opk, opk); err != nil { + t.Fatal(err) + } + if _, err := VPSHUFBITQMB(opm512, opzmm, opk); err != nil { + t.Fatal(err) + } +} + func TestVPSHUFB_ZValidFormsNoError(t *testing.T) { if _, err := VPSHUFB_Z(opm128, opxmm, opk, opxmm); err != nil { t.Fatal(err) diff --git a/x86/zoptab.go b/x86/zoptab.go index 4b0be14..69fa3fc 100644 --- a/x86/zoptab.go +++ b/x86/zoptab.go @@ -323,6 +323,8 @@ const ( isasAVX512VBMI isasAVX512IFMA_AVX512VL isasAVX512IFMA + isasAVX512BITALG_AVX512VL + isasAVX512BITALG isasAVX512VL_AVX512VPOPCNTDQ isasAVX512VPOPCNTDQ isasAVX512BW_AVX512F @@ -392,6 +394,8 @@ var isaslisttable = [][]string{ {"AVX512VBMI"}, {"AVX512IFMA", "AVX512VL"}, {"AVX512IFMA"}, + {"AVX512BITALG", "AVX512VL"}, + {"AVX512BITALG"}, {"AVX512VL", "AVX512VPOPCNTDQ"}, {"AVX512VPOPCNTDQ"}, {"AVX512BW", "AVX512F"}, @@ -1528,8 +1532,10 @@ const ( opcVPMULLW opcVPMULTISHIFTQB opcVPMULUDQ + opcVPOPCNTB opcVPOPCNTD opcVPOPCNTQ + opcVPOPCNTW opcVPOR opcVPORD opcVPORQ @@ -1547,6 +1553,7 @@ const ( opcVPSCATTERQD opcVPSCATTERQQ opcVPSHUFB + opcVPSHUFBITQMB opcVPSHUFD opcVPSHUFHW opcVPSHUFLW @@ -2828,8 +2835,10 @@ var opcstringtable = []string{ "VPMULLW", "VPMULTISHIFTQB", "VPMULUDQ", + "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", + "VPOPCNTW", "VPOR", "VPORD", "VPORQ", @@ -2847,6 +2856,7 @@ var opcstringtable = []string{ "VPSCATTERQD", "VPSCATTERQQ", "VPSHUFB", + "VPSHUFBITQMB", "VPSHUFD", "VPSHUFHW", "VPSHUFLW", @@ -11918,6 +11928,24 @@ var forms = []form{ {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, {opcVPMULUDQ, sffxsclsZ, 0, isasAVX512F, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, {opcVPMULUDQ, sffxsclsNIL, 0, isasAVX512F, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPOPCNTB, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPOPCNTB, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPOPCNTB, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPOPCNTB, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTB, sffxsclsZ, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTB, sffxsclsZ, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTB, sffxsclsNIL, 0, isasAVX512BITALG, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, {opcVPOPCNTD, sffxsclsNIL, 0, isasAVX512VL_AVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, {opcVPOPCNTD, sffxsclsZ, 0, isasAVX512VL_AVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, {opcVPOPCNTD, sffxsclsNIL, 0, isasAVX512VL_AVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, @@ -11972,6 +12000,24 @@ var forms = []form{ {opcVPOPCNTQ, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, {opcVPOPCNTQ, sffxsclsZ, 0, isasAVX512VPOPCNTDQ, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, {opcVPOPCNTQ, sffxsclsNIL, 0, isasAVX512VPOPCNTDQ, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPOPCNTW, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPOPCNTW, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPOPCNTW, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPOPCNTW, sffxsclsZ, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 2, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTW, sffxsclsZ, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG, 2, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPOPCNTW, sffxsclsZ, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPOPCNTW, sffxsclsNIL, 0, isasAVX512BITALG, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, {opcVPOR, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, {opcVPOR, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, {opcVPOR, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, @@ -12282,6 +12328,18 @@ var forms = []form{ {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, {opcVPSHUFB, sffxsclsZ, 0, isasAVX512BW, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, {opcVPSHUFB, sffxsclsNIL, 0, isasAVX512BW, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG_AVX512VL, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, + {opcVPSHUFBITQMB, sffxsclsNIL, 0, isasAVX512BITALG, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}}, {opcVPSHUFD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, {opcVPSHUFD, sffxsclsNIL, 0, isasAVX2, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, {opcVPSHUFD, sffxsclsNIL, 0, isasAVX, 3, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}}, @@ -15753,166 +15811,169 @@ var opcformstable = [][]form{ forms[8853:8871], forms[8871:8898], forms[8898:8925], - forms[8925:8952], - forms[8952:8979], - forms[8979:8983], - forms[8983:9010], - forms[9010:9037], - forms[9037:9064], - forms[9064:9091], - forms[9091:9118], - forms[9118:9145], - forms[9145:9172], - forms[9172:9199], - forms[9199:9226], - forms[9226:9253], - forms[9253:9259], - forms[9259:9262], - forms[9262:9265], - forms[9265:9268], - forms[9268:9271], - forms[9271:9289], - forms[9289:9316], - forms[9316:9334], - forms[9334:9352], - forms[9352:9356], - forms[9356:9360], - forms[9360:9364], - forms[9364:9409], - forms[9409:9415], - forms[9415:9460], - forms[9460:9487], - forms[9487:9514], - forms[9514:9532], - forms[9532:9568], - forms[9568:9613], - forms[9613:9658], - forms[9658:9685], - forms[9685:9712], - forms[9712:9730], - forms[9730:9766], - forms[9766:9811], - forms[9811:9817], - forms[9817:9862], - forms[9862:9889], - forms[9889:9916], - forms[9916:9934], - forms[9934:9970], - forms[9970:9988], - forms[9988:10015], - forms[10015:10042], - forms[10042:10060], - forms[10060:10078], - forms[10078:10096], - forms[10096:10114], - forms[10114:10132], - forms[10132:10159], - forms[10159:10186], - forms[10186:10190], - forms[10190:10202], - forms[10202:10220], - forms[10220:10238], + forms[8925:8943], + forms[8943:8970], + forms[8970:8997], + forms[8997:9015], + forms[9015:9019], + forms[9019:9046], + forms[9046:9073], + forms[9073:9100], + forms[9100:9127], + forms[9127:9154], + forms[9154:9181], + forms[9181:9208], + forms[9208:9235], + forms[9235:9262], + forms[9262:9289], + forms[9289:9295], + forms[9295:9298], + forms[9298:9301], + forms[9301:9304], + forms[9304:9307], + forms[9307:9325], + forms[9325:9337], + forms[9337:9364], + forms[9364:9382], + forms[9382:9400], + forms[9400:9404], + forms[9404:9408], + forms[9408:9412], + forms[9412:9457], + forms[9457:9463], + forms[9463:9508], + forms[9508:9535], + forms[9535:9562], + forms[9562:9580], + forms[9580:9616], + forms[9616:9661], + forms[9661:9706], + forms[9706:9733], + forms[9733:9760], + forms[9760:9778], + forms[9778:9814], + forms[9814:9859], + forms[9859:9865], + forms[9865:9910], + forms[9910:9937], + forms[9937:9964], + forms[9964:9982], + forms[9982:10018], + forms[10018:10036], + forms[10036:10063], + forms[10063:10090], + forms[10090:10108], + forms[10108:10126], + forms[10126:10144], + forms[10144:10162], + forms[10162:10180], + forms[10180:10207], + forms[10207:10234], + forms[10234:10238], forms[10238:10250], - forms[10250:10262], - forms[10262:10280], - forms[10280:10298], + forms[10250:10268], + forms[10268:10286], + forms[10286:10298], forms[10298:10310], forms[10310:10328], - forms[10328:10355], - forms[10355:10382], - forms[10382:10400], - forms[10400:10418], - forms[10418:10445], - forms[10445:10472], - forms[10472:10490], - forms[10490:10494], - forms[10494:10521], - forms[10521:10548], - forms[10548:10578], - forms[10578:10608], - forms[10608:10617], - forms[10617:10626], - forms[10626:10653], - forms[10653:10680], - forms[10680:10686], - forms[10686:10692], - forms[10692:10704], - forms[10704:10716], - forms[10716:10725], - forms[10725:10734], - forms[10734:10738], - forms[10738:10740], - forms[10740:10767], - forms[10767:10794], - forms[10794:10800], - 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