skeleton register package
This commit is contained in:
Michael McLoughlin
24
reg/reg_test.go
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24
reg/reg_test.go
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@@ -0,0 +1,24 @@
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package reg
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import "testing"
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func TestSpecBytes(t *testing.T) {
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cases := []struct {
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Spec Spec
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Bytes uint
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}{
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{S8L, 1},
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{S8H, 1},
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{S16, 2},
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{S32, 4},
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{S64, 8},
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{S128, 16},
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{S256, 32},
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{S512, 64},
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}
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for _, c := range cases {
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if c.Spec.Bytes() != c.Bytes {
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t.Errorf("%v.Bytes() = %d; expect = %d", c.Spec, c.Spec.Bytes(), c.Bytes)
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}
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}
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}
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109
reg/types.go
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109
reg/types.go
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package reg
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type Size uint
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const (
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B8 Size = 1 << iota
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B16
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B32
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B64
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B128
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B256
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B512
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)
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func (s Size) Bytes() uint { return uint(s) }
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type Kind uint8
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type Family struct {
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Kind Kind
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registers []Register
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}
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func (f *Family) define(s Spec, id uint16, name string) Register {
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r := register{
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id: id,
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kind: f.Kind,
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name: name,
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Spec: s,
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}
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f.registers = append(f.registers, r)
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return r
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}
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func (f *Family) Virtual(id uint16, s Size) Virtual {
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return virtual{
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id: id,
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kind: f.Kind,
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Size: s,
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}
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}
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type private interface {
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private()
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}
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type Virtual interface {
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VirtualID() uint16
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Kind() Kind
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Bytes() uint
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}
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type virtual struct {
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id uint16
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kind Kind
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Size
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}
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func (v virtual) VirtualID() uint16 { return v.id }
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func (v virtual) Kind() Kind { return v.kind }
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type Register interface {
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PhysicalID() uint16
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Kind() Kind
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Mask() uint16
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Bytes() uint
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Name() string
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private
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}
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type register struct {
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id uint16
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kind Kind
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name string
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Spec
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}
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func (r register) PhysicalID() uint16 { return r.id }
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func (r register) Kind() Kind { return r.kind }
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func (r register) Name() string { return r.name }
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func (r register) private() {}
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type Spec uint16
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const (
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S8L Spec = 0x1
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S8H Spec = 0x2
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S8 = S8L
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S16 Spec = 0x3
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S32 Spec = 0x7
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S64 Spec = 0xf
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S128 Spec = 0x1f
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S256 Spec = 0x3f
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S512 Spec = 0x7f
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)
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// Mask returns a mask representing which bytes of an underlying register are
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// used by this register. This is almost always the low bytes, except for the
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// case of the high-byte registers. If bit n of the mask is set, this means
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// bytes 2^(n-1) to 2^n-1 are used.
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func (s Spec) Mask() uint16 {
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return uint16(s)
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}
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// Bytes returns the register size in bytes.
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func (s Spec) Bytes() uint {
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x := uint(s)
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return (x >> 1) + (x & 1)
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}
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201
reg/x86.go
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201
reg/x86.go
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@@ -0,0 +1,201 @@
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package reg
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// Register families.
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const (
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GP Kind = iota
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MMX
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SSEAVX
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Mask
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)
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// General purpose registers.
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var (
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GeneralPurpose = &Family{Kind: GP}
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// Low byte
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AL = GeneralPurpose.define(S8L, 0, "AL")
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CL = GeneralPurpose.define(S8L, 1, "CL")
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DL = GeneralPurpose.define(S8L, 2, "DL")
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BL = GeneralPurpose.define(S8L, 3, "BL")
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// High byte
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AH = GeneralPurpose.define(S8H, 0, "AH")
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CH = GeneralPurpose.define(S8H, 1, "CH")
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DH = GeneralPurpose.define(S8H, 2, "DH")
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BH = GeneralPurpose.define(S8H, 3, "BH")
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// 8-bit
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SPB = GeneralPurpose.define(S8, 4, "SP")
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BPB = GeneralPurpose.define(S8, 5, "BP")
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SIB = GeneralPurpose.define(S8, 6, "SI")
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DIB = GeneralPurpose.define(S8, 7, "DI")
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R8B = GeneralPurpose.define(S8, 8, "R8")
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R9B = GeneralPurpose.define(S8, 9, "R9")
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R10B = GeneralPurpose.define(S8, 10, "R10")
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R11B = GeneralPurpose.define(S8, 11, "R11")
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R12B = GeneralPurpose.define(S8, 12, "R12")
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R13B = GeneralPurpose.define(S8, 13, "R13")
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R14B = GeneralPurpose.define(S8, 14, "R14")
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R15B = GeneralPurpose.define(S8, 15, "R15")
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// 16-bit
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AX = GeneralPurpose.define(S16, 0, "AX")
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CX = GeneralPurpose.define(S16, 1, "CX")
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DX = GeneralPurpose.define(S16, 2, "DX")
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BX = GeneralPurpose.define(S16, 3, "BX")
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SP = GeneralPurpose.define(S16, 4, "SP")
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BP = GeneralPurpose.define(S16, 5, "BP")
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SI = GeneralPurpose.define(S16, 6, "SI")
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DI = GeneralPurpose.define(S16, 7, "DI")
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R8W = GeneralPurpose.define(S16, 8, "R8")
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R9W = GeneralPurpose.define(S16, 9, "R9")
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R10W = GeneralPurpose.define(S16, 10, "R10")
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R11W = GeneralPurpose.define(S16, 11, "R11")
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R12W = GeneralPurpose.define(S16, 12, "R12")
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R13W = GeneralPurpose.define(S16, 13, "R13")
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R14W = GeneralPurpose.define(S16, 14, "R14")
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R15W = GeneralPurpose.define(S16, 15, "R15")
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// 32-bit
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EAX = GeneralPurpose.define(S32, 0, "AX")
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ECX = GeneralPurpose.define(S32, 1, "CX")
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EDX = GeneralPurpose.define(S32, 2, "DX")
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EBX = GeneralPurpose.define(S32, 3, "BX")
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ESP = GeneralPurpose.define(S32, 4, "SP")
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EBP = GeneralPurpose.define(S32, 5, "BP")
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ESI = GeneralPurpose.define(S32, 6, "SI")
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EDI = GeneralPurpose.define(S32, 7, "DI")
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R8L = GeneralPurpose.define(S32, 8, "R8")
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R9L = GeneralPurpose.define(S32, 9, "R9")
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R10L = GeneralPurpose.define(S32, 10, "R10")
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R11L = GeneralPurpose.define(S32, 11, "R11")
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R12L = GeneralPurpose.define(S32, 12, "R12")
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R13L = GeneralPurpose.define(S32, 13, "R13")
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R14L = GeneralPurpose.define(S32, 14, "R14")
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R15L = GeneralPurpose.define(S32, 15, "R15")
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// 64-bit
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RAX = GeneralPurpose.define(S64, 0, "AX")
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RCX = GeneralPurpose.define(S64, 1, "CX")
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RDX = GeneralPurpose.define(S64, 2, "DX")
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RBX = GeneralPurpose.define(S64, 3, "BX")
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RSP = GeneralPurpose.define(S64, 4, "SP")
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RBP = GeneralPurpose.define(S64, 5, "BP")
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RSI = GeneralPurpose.define(S64, 6, "SI")
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RDI = GeneralPurpose.define(S64, 7, "DI")
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R8 = GeneralPurpose.define(S64, 8, "R8")
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R9 = GeneralPurpose.define(S64, 9, "R9")
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R10 = GeneralPurpose.define(S64, 10, "R10")
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R11 = GeneralPurpose.define(S64, 11, "R11")
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R12 = GeneralPurpose.define(S64, 12, "R12")
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R13 = GeneralPurpose.define(S64, 13, "R13")
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R14 = GeneralPurpose.define(S64, 14, "R14")
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R15 = GeneralPurpose.define(S64, 15, "R15")
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)
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// SIMD registers.
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var (
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SIMD = &Family{Kind: SSEAVX}
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// 128-bit
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X0 = SIMD.define(S128, 0, "X0")
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X1 = SIMD.define(S128, 1, "X1")
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X2 = SIMD.define(S128, 2, "X2")
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X3 = SIMD.define(S128, 3, "X3")
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X4 = SIMD.define(S128, 4, "X4")
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X5 = SIMD.define(S128, 5, "X5")
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X6 = SIMD.define(S128, 6, "X6")
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X7 = SIMD.define(S128, 7, "X7")
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X8 = SIMD.define(S128, 8, "X8")
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X9 = SIMD.define(S128, 9, "X9")
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X10 = SIMD.define(S128, 10, "X10")
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X11 = SIMD.define(S128, 11, "X11")
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X12 = SIMD.define(S128, 12, "X12")
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X13 = SIMD.define(S128, 13, "X13")
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X14 = SIMD.define(S128, 14, "X14")
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X15 = SIMD.define(S128, 15, "X15")
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X16 = SIMD.define(S128, 16, "X16")
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X17 = SIMD.define(S128, 17, "X17")
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X18 = SIMD.define(S128, 18, "X18")
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X19 = SIMD.define(S128, 19, "X19")
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X20 = SIMD.define(S128, 20, "X20")
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X21 = SIMD.define(S128, 21, "X21")
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X22 = SIMD.define(S128, 22, "X22")
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X23 = SIMD.define(S128, 23, "X23")
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X24 = SIMD.define(S128, 24, "X24")
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X25 = SIMD.define(S128, 25, "X25")
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X26 = SIMD.define(S128, 26, "X26")
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X27 = SIMD.define(S128, 27, "X27")
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X28 = SIMD.define(S128, 28, "X28")
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X29 = SIMD.define(S128, 29, "X29")
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X30 = SIMD.define(S128, 30, "X30")
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X31 = SIMD.define(S128, 31, "X31")
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// 256-bit
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Y0 = SIMD.define(S256, 0, "Y0")
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Y1 = SIMD.define(S256, 1, "Y1")
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Y2 = SIMD.define(S256, 2, "Y2")
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Y3 = SIMD.define(S256, 3, "Y3")
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Y4 = SIMD.define(S256, 4, "Y4")
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Y5 = SIMD.define(S256, 5, "Y5")
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Y6 = SIMD.define(S256, 6, "Y6")
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Y7 = SIMD.define(S256, 7, "Y7")
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Y8 = SIMD.define(S256, 8, "Y8")
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Y9 = SIMD.define(S256, 9, "Y9")
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Y10 = SIMD.define(S256, 10, "Y10")
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Y11 = SIMD.define(S256, 11, "Y11")
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Y12 = SIMD.define(S256, 12, "Y12")
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Y13 = SIMD.define(S256, 13, "Y13")
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Y14 = SIMD.define(S256, 14, "Y14")
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Y15 = SIMD.define(S256, 15, "Y15")
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Y16 = SIMD.define(S256, 16, "Y16")
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Y17 = SIMD.define(S256, 17, "Y17")
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Y18 = SIMD.define(S256, 18, "Y18")
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Y19 = SIMD.define(S256, 19, "Y19")
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Y20 = SIMD.define(S256, 20, "Y20")
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Y21 = SIMD.define(S256, 21, "Y21")
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Y22 = SIMD.define(S256, 22, "Y22")
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Y23 = SIMD.define(S256, 23, "Y23")
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Y24 = SIMD.define(S256, 24, "Y24")
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Y25 = SIMD.define(S256, 25, "Y25")
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Y26 = SIMD.define(S256, 26, "Y26")
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Y27 = SIMD.define(S256, 27, "Y27")
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Y28 = SIMD.define(S256, 28, "Y28")
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Y29 = SIMD.define(S256, 29, "Y29")
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Y30 = SIMD.define(S256, 30, "Y30")
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Y31 = SIMD.define(S256, 31, "Y31")
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// 512-bit
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Z0 = SIMD.define(S512, 0, "Z0")
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Z1 = SIMD.define(S512, 1, "Z1")
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Z2 = SIMD.define(S512, 2, "Z2")
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Z3 = SIMD.define(S512, 3, "Z3")
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Z4 = SIMD.define(S512, 4, "Z4")
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Z5 = SIMD.define(S512, 5, "Z5")
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Z6 = SIMD.define(S512, 6, "Z6")
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Z7 = SIMD.define(S512, 7, "Z7")
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Z8 = SIMD.define(S512, 8, "Z8")
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Z9 = SIMD.define(S512, 9, "Z9")
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Z10 = SIMD.define(S512, 10, "Z10")
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Z11 = SIMD.define(S512, 11, "Z11")
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Z12 = SIMD.define(S512, 12, "Z12")
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Z13 = SIMD.define(S512, 13, "Z13")
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Z14 = SIMD.define(S512, 14, "Z14")
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Z15 = SIMD.define(S512, 15, "Z15")
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Z16 = SIMD.define(S512, 16, "Z16")
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Z17 = SIMD.define(S512, 17, "Z17")
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Z18 = SIMD.define(S512, 18, "Z18")
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Z19 = SIMD.define(S512, 19, "Z19")
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Z20 = SIMD.define(S512, 20, "Z20")
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Z21 = SIMD.define(S512, 21, "Z21")
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Z22 = SIMD.define(S512, 22, "Z22")
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Z23 = SIMD.define(S512, 23, "Z23")
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Z24 = SIMD.define(S512, 24, "Z24")
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Z25 = SIMD.define(S512, 25, "Z25")
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Z26 = SIMD.define(S512, 26, "Z26")
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Z27 = SIMD.define(S512, 27, "Z27")
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Z28 = SIMD.define(S512, 28, "Z28")
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Z29 = SIMD.define(S512, 29, "Z29")
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Z30 = SIMD.define(S512, 30, "Z30")
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Z31 = SIMD.define(S512, 31, "Z31")
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)
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