all: VPCLMULQDQ instruction (#360)

Adds VEX and EVEX encoded versions of the `PCLMULQDQ` carry-less quadword
multiplication instruction.

These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database.

Contributed by @vsivsi. Extracted from #349 with minor tweaks.

Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
This commit is contained in:
Michael McLoughlin
2023-01-09 21:38:43 -08:00
committed by GitHub
parent b893b32213
commit 7dac51aabf
7 changed files with 510 additions and 296 deletions

View File

@@ -66940,6 +66940,46 @@ var Instructions = []Instruction{
},
EncodingType: 0x3,
},
{
ISA: []string{"VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "m256", Action: 0x1},
{Type: "ymm", Action: 0x1},
{Type: "ymm", Action: 0x2},
},
EncodingType: 0x3,
},
{
ISA: []string{"VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "ymm", Action: 0x1},
{Type: "ymm", Action: 0x1},
{Type: "ymm", Action: 0x2},
},
EncodingType: 0x3,
},
{
ISA: []string{"AVX512F", "VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "m512", Action: 0x1},
{Type: "zmm", Action: 0x1},
{Type: "zmm", Action: 0x2},
},
EncodingType: 0x4,
},
{
ISA: []string{"AVX512F", "VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "zmm", Action: 0x1},
{Type: "zmm", Action: 0x1},
{Type: "zmm", Action: 0x2},
},
EncodingType: 0x4,
},
},
},
{