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all: VPCLMULQDQ instruction (#360)

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Adds VEX and EVEX encoded versions of the `PCLMULQDQ` carry-less quadword
multiplication instruction.

These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database.

Contributed by @vsivsi. Extracted from #349 with minor tweaks.

Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
This commit is contained in:
Michael McLoughlin
2023-01-09 21:38:43 -08:00
committed by GitHub
parent b893b32213
commit 7dac51aabf
7 changed files with 510 additions and 296 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
build/zinstructions.go
View File

@@ -58405,10 +58405,14 @@ func VPBROADCASTW_Z(mrx, k, xyz operand.Op) { ctx.VPBROADCASTW_Z(mrx, k, xyz) }
//
// VPCLMULQDQ imm8 m128 xmm xmm
// VPCLMULQDQ imm8 xmm xmm xmm
// VPCLMULQDQ imm8 m256 ymm ymm
// VPCLMULQDQ imm8 ymm ymm ymm
// VPCLMULQDQ imm8 m512 zmm zmm
// VPCLMULQDQ imm8 zmm zmm zmm
//
// Construct and append a VPCLMULQDQ instruction to the active function.
func (c *Context) VPCLMULQDQ(i, mx, x, x1 operand.Op) {
c.addinstruction(x86.VPCLMULQDQ(i, mx, x, x1))
func (c *Context) VPCLMULQDQ(i, mxyz, xyz, xyz1 operand.Op) {
c.addinstruction(x86.VPCLMULQDQ(i, mxyz, xyz, xyz1))
}
// VPCLMULQDQ: Carry-Less Quadword Multiplication.
@@ -58417,10 +58421,14 @@ func (c *Context) VPCLMULQDQ(i, mx, x, x1 operand.Op) {
//
// VPCLMULQDQ imm8 m128 xmm xmm
// VPCLMULQDQ imm8 xmm xmm xmm
// VPCLMULQDQ imm8 m256 ymm ymm
// VPCLMULQDQ imm8 ymm ymm ymm
// VPCLMULQDQ imm8 m512 zmm zmm
// VPCLMULQDQ imm8 zmm zmm zmm
//
// Construct and append a VPCLMULQDQ instruction to the active function.
// Operates on the global context.
func VPCLMULQDQ(i, mx, x, x1 operand.Op) { ctx.VPCLMULQDQ(i, mx, x, x1) }
func VPCLMULQDQ(i, mxyz, xyz, xyz1 operand.Op) { ctx.VPCLMULQDQ(i, mxyz, xyz, xyz1) }
// VPCMPB: Compare Packed Signed Byte Values.
//

40
internal/inst/ztable.go
View File

@@ -66940,6 +66940,46 @@ var Instructions = []Instruction{
},
EncodingType: 0x3,
},
{
ISA: []string{"VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "m256", Action: 0x1},
{Type: "ymm", Action: 0x1},
{Type: "ymm", Action: 0x2},
},
EncodingType: 0x3,
},
{
ISA: []string{"VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "ymm", Action: 0x1},
{Type: "ymm", Action: 0x1},
{Type: "ymm", Action: 0x2},
},
EncodingType: 0x3,
},
{
ISA: []string{"AVX512F", "VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "m512", Action: 0x1},
{Type: "zmm", Action: 0x1},
{Type: "zmm", Action: 0x2},
},
EncodingType: 0x4,
},
{
ISA: []string{"AVX512F", "VPCLMULQDQ"},
Operands: []Operand{
{Type: "imm8", Action: 0x0},
{Type: "zmm", Action: 0x1},
{Type: "zmm", Action: 0x1},
{Type: "zmm", Action: 0x2},
},
EncodingType: 0x4,
},
},
},
{

1
internal/opcodesextra/instructions.go
View File

@@ -9,6 +9,7 @@ var sets = [][]*inst.Instruction{
gfni,
vaes,
vnni,
vpclmulqdq,
}
// Instructions returns a list of extras to add to the instructions database.

141
internal/opcodesextra/vpclmulqdq.go Normal file
View File

@@ -0,0 +1,141 @@
package opcodesextra
import "github.com/mmcloughlin/avo/internal/inst"
// vpclmulqdq adds VEX and EVEX encoded versions of the PCLMULQDQ carry-less
// quadword multiplication instruction.
var vpclmulqdq = []*inst.Instruction{
// Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L2911-L2917
//
// {as: AVPCLMULQDQ, ytab: _yvpclmulqdq, prefix: Pavx, op: opBytes{
// avxEscape | vex128 | vex66 | vex0F3A | vexW0, 0x44,
// avxEscape | vex256 | vex66 | vex0F3A | vexW0, 0x44,
// avxEscape | evex128 | evex66 | evex0F3A | evexW0, evexN16, 0x44,
// avxEscape | evex256 | evex66 | evex0F3A | evexW0, evexN32, 0x44,
// avxEscape | evex512 | evex66 | evex0F3A | evexW0, evexN64, 0x44,
// }},
//
{
Opcode: "VPCLMULQDQ",
Summary: "Carry-Less Quadword Multiplication",
// See: https://www.felixcloutier.com/x86/pclmulqdq
//
// Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L676-L682
//
// var _yvpclmulqdq = []ytab{
// {zcase: Zvex_i_rm_v_r, zoffset: 2, args: argList{Yu8, Yxm, Yxr, Yxr}},
// {zcase: Zvex_i_rm_v_r, zoffset: 2, args: argList{Yu8, Yym, Yyr, Yyr}},
// {zcase: Zevex_i_rm_v_r, zoffset: 3, args: argList{Yu8, YxmEvex, YxrEvex, YxrEvex}},
// {zcase: Zevex_i_rm_v_r, zoffset: 3, args: argList{Yu8, YymEvex, YyrEvex, YyrEvex}},
// {zcase: Zevex_i_rm_v_r, zoffset: 3, args: argList{Yu8, Yzm, Yzr, Yzr}},
// }
//
Forms: inst.Forms{
// VEX.128.66.0F3A.WIG 44 /r ib VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8
{
ISA: []string{"AVX", "PCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "m128", Action: inst.R},
{Type: "xmm", Action: inst.R},
{Type: "xmm", Action: inst.W},
},
EncodingType: inst.EncodingTypeVEX,
},
{
ISA: []string{"AVX", "PCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "xmm", Action: inst.R},
{Type: "xmm", Action: inst.R},
{Type: "xmm", Action: inst.W},
},
EncodingType: inst.EncodingTypeVEX,
},
// VEX.256.66.0F3A.WIG 44 /r /ib VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8
{
ISA: []string{"VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "m256", Action: inst.R},
{Type: "ymm", Action: inst.R},
{Type: "ymm", Action: inst.W},
},
EncodingType: inst.EncodingTypeVEX,
},
{
ISA: []string{"VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "ymm", Action: inst.R},
{Type: "ymm", Action: inst.R},
{Type: "ymm", Action: inst.W},
},
EncodingType: inst.EncodingTypeVEX,
},
// EVEX.128.66.0F3A.WIG 44 /r /ib VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8
{
ISA: []string{"AVX512VL", "VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "m128", Action: inst.R},
{Type: "xmm", Action: inst.R},
{Type: "xmm", Action: inst.W},
},
EncodingType: inst.EncodingTypeEVEX,
},
{
ISA: []string{"AVX512VL", "VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "xmm", Action: inst.R},
{Type: "xmm", Action: inst.R},
{Type: "xmm", Action: inst.W},
},
EncodingType: inst.EncodingTypeEVEX,
},
// EVEX.256.66.0F3A.WIG 44 /r /ib VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8
{
ISA: []string{"AVX512VL", "VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "m256", Action: inst.R},
{Type: "ymm", Action: inst.R},
{Type: "ymm", Action: inst.W},
},
EncodingType: inst.EncodingTypeEVEX,
},
{
ISA: []string{"AVX512VL", "VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "ymm", Action: inst.R},
{Type: "ymm", Action: inst.R},
{Type: "ymm", Action: inst.W},
},
EncodingType: inst.EncodingTypeEVEX,
},
// EVEX.512.66.0F3A.WIG 44 /r /ib VPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8
{
ISA: []string{"AVX512F", "VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "m512", Action: inst.R},
{Type: "zmm", Action: inst.R},
{Type: "zmm", Action: inst.W},
},
EncodingType: inst.EncodingTypeEVEX,
},
{
ISA: []string{"AVX512F", "VPCLMULQDQ"},
Operands: []inst.Operand{
{Type: "imm8"},
{Type: "zmm", Action: inst.R},
{Type: "zmm", Action: inst.R},
{Type: "zmm", Action: inst.W},
},
EncodingType: inst.EncodingTypeEVEX,
},
},
},
}

8
x86/zctors.go
View File

@@ -25753,8 +25753,12 @@ func VPBROADCASTW_Z(mrx, k, xyz operand.Op) (*intrep.Instruction, error) {
//
// VPCLMULQDQ imm8 m128 xmm xmm
// VPCLMULQDQ imm8 xmm xmm xmm
func VPCLMULQDQ(i, mx, x, x1 operand.Op) (*intrep.Instruction, error) {
return build(opcVPCLMULQDQ.Forms(), sffxs{}, []operand.Op{i, mx, x, x1})
// VPCLMULQDQ imm8 m256 ymm ymm
// VPCLMULQDQ imm8 ymm ymm ymm
// VPCLMULQDQ imm8 m512 zmm zmm
// VPCLMULQDQ imm8 zmm zmm zmm
func VPCLMULQDQ(i, mxyz, xyz, xyz1 operand.Op) (*intrep.Instruction, error) {
return build(opcVPCLMULQDQ.Forms(), sffxs{}, []operand.Op{i, mxyz, xyz, xyz1})
}
// VPCMPB: Compare Packed Signed Byte Values.

12
x86/zctors_test.go
View File

@@ -29001,6 +29001,18 @@ func TestVPCLMULQDQValidFormsNoError(t *testing.T) {
if _, err := VPCLMULQDQ(opimm8, opxmm, opxmm, opxmm); err != nil {
t.Fatal(err)
}
if _, err := VPCLMULQDQ(opimm8, opm256, opymm, opymm); err != nil {
t.Fatal(err)
}
if _, err := VPCLMULQDQ(opimm8, opymm, opymm, opymm); err != nil {
t.Fatal(err)
}
if _, err := VPCLMULQDQ(opimm8, opm512, opzmm, opzmm); err != nil {
t.Fatal(err)
}
if _, err := VPCLMULQDQ(opimm8, opzmm, opzmm, opzmm); err != nil {
t.Fatal(err)
}
}
func TestVPCMPBValidFormsNoError(t *testing.T) {

590
x86/zoptab.go
View File

@@ -315,6 +315,8 @@ const (
isasAVX512CD_AVX512VL
isasAVX512CD
isasAVX_PCLMULQDQ
isasVPCLMULQDQ
isasAVX512F_VPCLMULQDQ
isasAVX512VL_AVX512VNNI
isasAVX512VNNI
isasAVX512VBMI_AVX512VL
@@ -381,6 +383,8 @@ var isaslisttable = [][]string{
{"AVX512CD", "AVX512VL"},
{"AVX512CD"},
{"AVX", "PCLMULQDQ"},
{"VPCLMULQDQ"},
{"AVX512F", "VPCLMULQDQ"},
{"AVX512VL", "AVX512VNNI"},
{"AVX512VNNI"},
{"AVX512VBMI", "AVX512VL"},
@@ -9503,6 +9507,10 @@ var forms = []form{
{opcVPBROADCASTW, sffxsclsNIL, 0, isasAVX512BW, 2, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}},
{opcVPCLMULQDQ, sffxsclsNIL, 0, isasAVX_PCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}},
{opcVPCLMULQDQ, sffxsclsNIL, 0, isasAVX_PCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionW}}},
{opcVPCLMULQDQ, sffxsclsNIL, 0, isasVPCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}},
{opcVPCLMULQDQ, sffxsclsNIL, 0, isasVPCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}},
{opcVPCLMULQDQ, sffxsclsNIL, 0, isasAVX512F_VPCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}},
{opcVPCLMULQDQ, sffxsclsNIL, 0, isasAVX512F_VPCLMULQDQ, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}},
{opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}},
{opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionW}}},
{opcVPCMPB, sffxsclsNIL, 0, isasAVX512BW_AVX512VL, 5, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeK), false, actionW}}},
@@ -15563,310 +15571,310 @@ var opcformstable = [][]form{
forms[6457:6460],
forms[6460:6487],
forms[6487:6514],
forms[6514:6516],
forms[6516:6528],
forms[6528:6546],
forms[6546:6562],
forms[6562:6584],
forms[6584:6606],
forms[6606:6622],
forms[6622:6624],
forms[6624:6626],
forms[6626:6642],
forms[6642:6664],
forms[6664:6686],
forms[6686:6702],
forms[6702:6704],
forms[6704:6706],
forms[6706:6724],
forms[6724:6736],
forms[6736:6754],
forms[6754:6772],
forms[6772:6784],
forms[6784:6796],
forms[6796:6814],
forms[6814:6832],
forms[6832:6859],
forms[6859:6886],
forms[6886:6913],
forms[6913:6940],
forms[6940:6967],
forms[6967:6994],
forms[6994:6996],
forms[6996:6998],
forms[6998:7016],
forms[7016:7034],
forms[7034:7052],
forms[7052:7079],
forms[7079:7106],
forms[7106:7133],
forms[7133:7160],
forms[7160:7178],
forms[7178:7232],
forms[7232:7286],
forms[7286:7322],
forms[7322:7340],
forms[7340:7376],
forms[7376:7394],
forms[7394:7421],
forms[7421:7448],
forms[7448:7475],
forms[7475:7502],
forms[7502:7520],
forms[7520:7538],
forms[7538:7556],
forms[7556:7574],
forms[7574:7576],
forms[7576:7578],
forms[6514:6520],
forms[6520:6532],
forms[6532:6550],
forms[6550:6566],
forms[6566:6588],
forms[6588:6610],
forms[6610:6626],
forms[6626:6628],
forms[6628:6630],
forms[6630:6646],
forms[6646:6668],
forms[6668:6690],
forms[6690:6706],
forms[6706:6708],
forms[6708:6710],
forms[6710:6728],
forms[6728:6740],
forms[6740:6758],
forms[6758:6776],
forms[6776:6788],
forms[6788:6800],
forms[6800:6818],
forms[6818:6836],
forms[6836:6863],
forms[6863:6890],
forms[6890:6917],
forms[6917:6944],
forms[6944:6971],
forms[6971:6998],
forms[6998:7000],
forms[7000:7002],
forms[7002:7020],
forms[7020:7038],
forms[7038:7056],
forms[7056:7083],
forms[7083:7110],
forms[7110:7137],
forms[7137:7164],
forms[7164:7182],
forms[7182:7236],
forms[7236:7290],
forms[7290:7326],
forms[7326:7344],
forms[7344:7380],
forms[7380:7398],
forms[7398:7425],
forms[7425:7452],
forms[7452:7479],
forms[7479:7506],
forms[7506:7524],
forms[7524:7542],
forms[7542:7560],
forms[7560:7578],
forms[7578:7580],
forms[7580:7582],
forms[7582:7587],
forms[7587:7592],
forms[7592:7597],
forms[7597:7602],
forms[7602:7606],
forms[7582:7584],
forms[7584:7586],
forms[7586:7591],
forms[7591:7596],
forms[7596:7601],
forms[7601:7606],
forms[7606:7610],
forms[7610:7614],
forms[7614:7616],
forms[7616:7620],
forms[7614:7618],
forms[7618:7620],
forms[7620:7624],
forms[7624:7628],
forms[7628:7630],
forms[7630:7632],
forms[7628:7632],
forms[7632:7634],
forms[7634:7636],
forms[7636:7663],
forms[7663:7690],
forms[7690:7717],
forms[7717:7744],
forms[7744:7762],
forms[7762:7780],
forms[7780:7784],
forms[7636:7638],
forms[7638:7640],
forms[7640:7667],
forms[7667:7694],
forms[7694:7721],
forms[7721:7748],
forms[7748:7766],
forms[7766:7784],
forms[7784:7788],
forms[7788:7806],
forms[7806:7833],
forms[7833:7860],
forms[7860:7878],
forms[7878:7896],
forms[7896:7923],
forms[7923:7950],
forms[7950:7968],
forms[7968:7986],
forms[7986:8013],
forms[8013:8040],
forms[8040:8058],
forms[8058:8076],
forms[8076:8103],
forms[8103:8130],
forms[8130:8148],
forms[8148:8151],
forms[8151:8154],
forms[8154:8172],
forms[8172:8190],
forms[8190:8193],
forms[8193:8196],
forms[8196:8199],
forms[8199:8202],
forms[8202:8204],
forms[8204:8207],
forms[8207:8225],
forms[8225:8243],
forms[8243:8261],
forms[8261:8279],
forms[8279:8297],
forms[8297:8315],
forms[8315:8333],
forms[8333:8351],
forms[8351:8369],
forms[8369:8387],
forms[8387:8405],
forms[8405:8423],
forms[8423:8441],
forms[8441:8459],
forms[8459:8477],
forms[8477:8495],
forms[8495:8513],
forms[8513:8531],
forms[8531:8549],
forms[8549:8567],
forms[8567:8585],
forms[8585:8588],
forms[8588:8606],
forms[8606:8624],
forms[8624:8642],
forms[8642:8660],
forms[8660:8678],
forms[8678:8696],
forms[8696:8714],
forms[8714:8741],
forms[8741:8759],
forms[8759:8777],
forms[8777:8795],
forms[8795:8822],
forms[8822:8849],
forms[8849:8867],
forms[8867:8894],
forms[8894:8921],
forms[8921:8930],
forms[8930:8939],
forms[8939:8943],
forms[8943:8970],
forms[8970:8997],
forms[8997:9024],
forms[9024:9051],
forms[9051:9078],
forms[9078:9105],
forms[9105:9132],
forms[9132:9159],
forms[9159:9186],
forms[9186:9213],
forms[9213:9219],
forms[9219:9222],
forms[9222:9225],
forms[9225:9228],
forms[9228:9231],
forms[9231:9249],
forms[9249:9276],
forms[9276:9294],
forms[9294:9312],
forms[9312:9316],
forms[7788:7792],
forms[7792:7810],
forms[7810:7837],
forms[7837:7864],
forms[7864:7882],
forms[7882:7900],
forms[7900:7927],
forms[7927:7954],
forms[7954:7972],
forms[7972:7990],
forms[7990:8017],
forms[8017:8044],
forms[8044:8062],
forms[8062:8080],
forms[8080:8107],
forms[8107:8134],
forms[8134:8152],
forms[8152:8155],
forms[8155:8158],
forms[8158:8176],
forms[8176:8194],
forms[8194:8197],
forms[8197:8200],
forms[8200:8203],
forms[8203:8206],
forms[8206:8208],
forms[8208:8211],
forms[8211:8229],
forms[8229:8247],
forms[8247:8265],
forms[8265:8283],
forms[8283:8301],
forms[8301:8319],
forms[8319:8337],
forms[8337:8355],
forms[8355:8373],
forms[8373:8391],
forms[8391:8409],
forms[8409:8427],
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