code/avo
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

all: AVX-512 (#217)

Browse Source 
Extends avo to support most AVX-512 instruction sets.

The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.

Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.

AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:

1.  Instruction constructors in the `x86` package moved to an optab-based
    approach. This compiles substantially faster than the verbose code
    generation we had before.

2.  The most verbose code-generated tests are moved under build tags and
    limited to a stress test mode. Stress test builds are run on
    schedule but not in regular CI.

An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.

Updates #20 #163 #229

Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
This commit is contained in:
Michael McLoughlin
2021-11-12 18:35:36 -08:00
parent 2867bd7e01
commit b76e849b5c
71 changed files with 257395 additions and 61474 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
internal/load/tables.go
View File

@@ -95,6 +95,54 @@ func init() {
aliases = append(aliases, annoyingaliases...)
}
// maskrequired is a set of AVX-512 opcodes where the mask register is required.
// Usually the mask register can be omitted, in which case K0 is implied.
var maskrequired = map[string]bool{
// Reference: https://github.com/golang/go/blob/4fd94558820100129b98f284e21b19fc27a99926/src/cmd/internal/obj/x86/asm6.go#L4219-L4240
//
// // Checks to warn about instruction/arguments combinations that
// // will unconditionally trigger illegal instruction trap (#UD).
// switch p.As {
// case AVGATHERDPD,
// AVGATHERQPD,
// AVGATHERDPS,
// AVGATHERQPS,
// AVPGATHERDD,
// AVPGATHERQD,
// AVPGATHERDQ,
// AVPGATHERQQ:
// // AVX512 gather requires explicit K mask.
// if p.GetFrom3().Reg >= REG_K0 && p.GetFrom3().Reg <= REG_K7 {
// if !avx512gatherValid(ctxt, p) {
// return
// }
// } else {
// if !avx2gatherValid(ctxt, p) {
// return
// }
// }
// }
//
"VGATHERDPD": true,
"VGATHERQPD": true,
"VGATHERDPS": true,
"VGATHERQPS": true,
"VPGATHERDD": true,
"VPGATHERQD": true,
"VPGATHERDQ": true,
"VPGATHERQQ": true,
// Restriction applies to SCATTER instructions too.
"VPSCATTERDD": true,
"VPSCATTERDQ": true,
"VPSCATTERQD": true,
"VPSCATTERQQ": true,
"VSCATTERDPD": true,
"VSCATTERDPS": true,
"VSCATTERQPD": true,
"VSCATTERQPS": true,
}
// extras is simply a list of extra instructions to add to the database.
var extras = []*inst.Instruction{
// MOVLQZX does not appear in either x86 CSV or Opcodes, but does appear in stdlib assembly.