all: AVX-512 (#217)

Extends avo to support most AVX-512 instruction sets.

The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.

Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.

AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:

1.  Instruction constructors in the `x86` package moved to an optab-based
    approach. This compiles substantially faster than the verbose code
    generation we had before.

2.  The most verbose code-generated tests are moved under build tags and
    limited to a stress test mode. Stress test builds are run on
    schedule but not in regular CI.

An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.

Updates #20 #163 #229

Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>

operand/checks.go

@@ -131,6 +131,16 @@ func IsYMM(op Op) bool {
 	return IsRegisterKindSize(op, reg.KindVector, 32)
 }
 
+// IsZMM returns true if op is a 512-bit ZMM register.
+func IsZMM(op Op) bool {
+	return IsRegisterKindSize(op, reg.KindVector, 64)
+}
+
+// IsK returns true if op is an Opmask register.
+func IsK(op Op) bool {
+	return IsRegisterKind(op, reg.KindOpmask)
+}
+
 // IsRegisterKindSize returns true if op is a register of the given kind and size in bytes.
 func IsRegisterKindSize(op Op, k reg.Kind, n uint) bool {
 	r, ok := op.(reg.Register)
@@ -200,6 +210,12 @@ func IsM256(op Op) bool {
 	return IsM64(op)
 }
 
+// IsM512 returns true if op is a 512-bit memory operand.
+func IsM512(op Op) bool {
+	// TODO(mbm): should "m512" be the same as "m64"?
+	return IsM64(op)
+}
+
 // IsVM32X returns true if op is a vector memory operand with 32-bit XMM index.
 func IsVM32X(op Op) bool {
 	return IsVmx(op)
@@ -230,6 +246,21 @@ func IsVmy(op Op) bool {
 	return isvm(op, IsYMM)
 }
 
+// IsVM32Z returns true if op is a vector memory operand with 32-bit ZMM index.
+func IsVM32Z(op Op) bool {
+	return IsVmz(op)
+}
+
+// IsVM64Z returns true if op is a vector memory operand with 64-bit ZMM index.
+func IsVM64Z(op Op) bool {
+	return IsVmz(op)
+}
+
+// IsVmz returns true if op is a vector memory operand with ZMM index.
+func IsVmz(op Op) bool {
+	return isvm(op, IsZMM)
+}
+
 func isvm(op Op, idx func(Op) bool) bool {
 	m, ok := op.(Mem)
 	return ok && IsR64(m.Base) && idx(m.Index)

operand/checks_test.go

@@ -127,6 +127,9 @@ func TestChecks(t *testing.T) {
 		{IsM256, Mem{Base: reg.RBX, Index: reg.R12, Scale: 2}, true},
 		{IsM256, Mem{Base: reg.X0}, false},
 
+		{IsM512, Mem{Base: reg.RBX, Index: reg.R12, Scale: 2}, true},
+		{IsM512, Mem{Base: reg.X0}, false},
+
 		// Argument references (special cases of memory operands)
 		{IsM, NewParamAddr("foo", 4), true},
 		{IsM8, NewParamAddr("foo", 4), true},
@@ -151,6 +154,14 @@ func TestChecks(t *testing.T) {
 		{IsVM64Y, Mem{Base: reg.R11L, Index: reg.Y11}, false},
 		{IsVM64Y, Mem{Base: reg.R8, Index: reg.Z11}, false},
 
+		{IsVM32Z, Mem{Base: reg.R9, Index: reg.Z11}, true},
+		{IsVM32Z, Mem{Base: reg.R11L, Index: reg.Z11}, false},
+		{IsVM32Z, Mem{Base: reg.R8, Index: reg.Y11}, false},
+
+		{IsVM64Z, Mem{Base: reg.R9, Index: reg.Z11}, true},
+		{IsVM64Z, Mem{Base: reg.R11L, Index: reg.Z11}, false},
+		{IsVM64Z, Mem{Base: reg.R8, Index: reg.X11}, false},
+
 		// Relative operands
 		{IsREL8, Rel(math.MinInt8), true},
 		{IsREL8, Rel(math.MaxInt8), true},