all: AVX-512 (#217)
Extends avo to support most AVX-512 instruction sets.
The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.
Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.
AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:
1. Instruction constructors in the `x86` package moved to an optab-based
approach. This compiles substantially faster than the verbose code
generation we had before.
2. The most verbose code-generated tests are moved under build tags and
limited to a stress test mode. Stress test builds are run on
schedule but not in regular CI.
An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.
Updates #20 #163 #229
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
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@@ -127,6 +127,9 @@ func TestChecks(t *testing.T) {
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{IsM256, Mem{Base: reg.RBX, Index: reg.R12, Scale: 2}, true},
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{IsM256, Mem{Base: reg.X0}, false},
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{IsM512, Mem{Base: reg.RBX, Index: reg.R12, Scale: 2}, true},
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{IsM512, Mem{Base: reg.X0}, false},
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// Argument references (special cases of memory operands)
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{IsM, NewParamAddr("foo", 4), true},
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{IsM8, NewParamAddr("foo", 4), true},
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@@ -151,6 +154,14 @@ func TestChecks(t *testing.T) {
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{IsVM64Y, Mem{Base: reg.R11L, Index: reg.Y11}, false},
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{IsVM64Y, Mem{Base: reg.R8, Index: reg.Z11}, false},
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{IsVM32Z, Mem{Base: reg.R9, Index: reg.Z11}, true},
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{IsVM32Z, Mem{Base: reg.R11L, Index: reg.Z11}, false},
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{IsVM32Z, Mem{Base: reg.R8, Index: reg.Y11}, false},
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{IsVM64Z, Mem{Base: reg.R9, Index: reg.Z11}, true},
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{IsVM64Z, Mem{Base: reg.R11L, Index: reg.Z11}, false},
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{IsVM64Z, Mem{Base: reg.R8, Index: reg.X11}, false},
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// Relative operands
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{IsREL8, Rel(math.MinInt8), true},
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{IsREL8, Rel(math.MaxInt8), true},
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