all: AVX-512 (#217)

Extends avo to support most AVX-512 instruction sets.

The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.

Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.

AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:

1.  Instruction constructors in the `x86` package moved to an optab-based
    approach. This compiles substantially faster than the verbose code
    generation we had before.

2.  The most verbose code-generated tests are moved under build tags and
    limited to a stress test mode. Stress test builds are run on
    schedule but not in regular CI.

An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.

Updates #20 #163 #229

Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>

reg/x86.go

@@ -5,6 +5,7 @@ const (
 	KindPseudo Kind = iota
 	KindGP
 	KindVector
+	KindOpmask
 )
 
 // Declare register families.
@@ -12,11 +13,13 @@ var (
 	Pseudo         = &Family{Kind: KindPseudo}
 	GeneralPurpose = &Family{Kind: KindGP}
 	Vector         = &Family{Kind: KindVector}
+	Opmask         = &Family{Kind: KindOpmask}
 
 	Families = []*Family{
 		Pseudo,
 		GeneralPurpose,
 		Vector,
+		Opmask,
 	}
 )
 
@@ -329,3 +332,52 @@ var (
 	Z30 = vec(S512, 30, "Z30")
 	Z31 = vec(S512, 31, "Z31")
 )
+
+// OpmaskPhysical is a opmask physical register.
+type OpmaskPhysical interface {
+	Physical
+}
+
+type opmaskp struct {
+	Physical
+}
+
+func newopmaskp(r Physical) OpmaskPhysical { return opmaskp{Physical: r} }
+
+// OpmaskVirtual is a virtual opmask register.
+type OpmaskVirtual interface {
+	Virtual
+}
+
+type opmaskv struct {
+	Virtual
+}
+
+func newopmaskv(v Virtual) OpmaskVirtual { return opmaskv{Virtual: v} }
+
+func opmask(s Spec, id Index, name string, flags ...Info) OpmaskPhysical {
+	r := newopmaskp(newregister(Opmask, s, id, name, flags...))
+	Opmask.add(r)
+	return r
+}
+
+// Opmask registers.
+//
+// Note that while K0 is a physical opmask register (it is a valid opmask source
+// and destination operand), it cannot be used as an opmask predicate value
+// because in that context K0 means "all true" or "no mask" regardless of the
+// actual contents of the physical register. For that reason, K0 should never be
+// assigned as a "general purpose" opmask register. However, it can be
+// explicitly operated upon by name as non-predicate operand, for example to
+// hold a constant or temporary value during calculations on other opmask
+// registers.
+var (
+	K0 = opmask(S64, 0, "K0", Restricted)
+	K1 = opmask(S64, 1, "K1")
+	K2 = opmask(S64, 2, "K2")
+	K3 = opmask(S64, 3, "K3")
+	K4 = opmask(S64, 4, "K4")
+	K5 = opmask(S64, 5, "K5")
+	K6 = opmask(S64, 6, "K6")
+	K7 = opmask(S64, 7, "K7")
+)