reg,pass: refactor allocation of aliased registers (#121)

Issue #100 demonstrated that register allocation for aliased registers is
fundamentally broken. The root of the issue is that currently accesses to the
same virtual register with different masks are treated as different registers.
This PR takes a different approach:

* Liveness analysis is masked: we now properly consider which parts of a register are live
* Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later

In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended).

Closes #100

tests/alloc/masks/asm.go

@@ -0,0 +1,66 @@
+// +build ignore
+
+package main
+
+import (
+	"strconv"
+
+	. "github.com/mmcloughlin/avo/build"
+	. "github.com/mmcloughlin/avo/operand"
+	. "github.com/mmcloughlin/avo/reg"
+)
+
+// The goal of this test is to create a synthetic scenario in which register
+// allocation would fail if register liveness and allocation passes didn't take
+// masks into account.
+//
+// The idea is to create a set of 15 64-bit virtual registers (15 being total
+// number of allocatable 64-bit general purpose registers). For each one: write
+// to the whole register and then later write to only the low 16 bits, and
+// finally consume the whole 64-bit register. This means there is an interval in
+// which only the high 48-bits are live. During this interval we should be able
+// to allocate and use a set of 15 16-bit virtual registers.
+
+func main() {
+	const n = 15
+
+	TEXT("Masks", NOSPLIT, "func() (uint16, uint64)")
+	Doc("Masks computes the sum 1+2+...+" + strconv.Itoa(n) + " in two ways.")
+
+	// Step 1: Allocate n 64-bit registers A that we will arrange to live in their top 48 bits.
+	A := make([]GPVirtual, n)
+	for i := 0; i < n; i++ {
+		A[i] = GP64()
+		c := ((i + 1) << 16) | 42 // 42 in low bits will be cleared later
+		MOVQ(U32(c), A[i])
+	}
+
+	// Step 3: Allocate n 16-bit registers B.
+	B := make([]Register, n)
+	for i := 0; i < n; i++ {
+		B[i] = GP16()
+		MOVW(U16(i+1), B[i])
+	}
+
+	// Step 3: Sum up all the B registers and return.
+	for i := 1; i < n; i++ {
+		ADDW(B[i], B[0])
+	}
+	Store(B[0], ReturnIndex(0))
+
+	// Step 4: Clear the low 16-bits of the A registers.
+	for i := 0; i < n; i++ {
+		MOVW(U16(0), A[i].As16())
+	}
+
+	// Step 5: Sum up all the A registers and return.
+	for i := 1; i < n; i++ {
+		ADDQ(A[i], A[0])
+	}
+	SHRQ(U8(16), A[0])
+	Store(A[0], ReturnIndex(1))
+
+	RET()
+
+	Generate()
+}

tests/alloc/masks/doc.go

@@ -0,0 +1,2 @@
+// Package masks tests that register liveness and allocation passes handle masks correctly.
+package masks

tests/alloc/masks/masks.s

@@ -0,0 +1,83 @@
+// Code generated by command: go run asm.go -out masks.s -stubs stub.go. DO NOT EDIT.
+
+#include "textflag.h"
+
+// func Masks() (uint16, uint64)
+TEXT ·Masks(SB), NOSPLIT, $0-16
+	MOVQ $0x0001002a, AX
+	MOVQ $0x0002002a, CX
+	MOVQ $0x0003002a, DX
+	MOVQ $0x0004002a, BX
+	MOVQ $0x0005002a, BP
+	MOVQ $0x0006002a, SI
+	MOVQ $0x0007002a, DI
+	MOVQ $0x0008002a, R8
+	MOVQ $0x0009002a, R9
+	MOVQ $0x000a002a, R10
+	MOVQ $0x000b002a, R11
+	MOVQ $0x000c002a, R12
+	MOVQ $0x000d002a, R13
+	MOVQ $0x000e002a, R14
+	MOVQ $0x000f002a, R15
+	MOVW $0x0001, AX
+	MOVW $0x0002, CX
+	MOVW $0x0003, DX
+	MOVW $0x0004, BX
+	MOVW $0x0005, BP
+	MOVW $0x0006, SI
+	MOVW $0x0007, DI
+	MOVW $0x0008, R8
+	MOVW $0x0009, R9
+	MOVW $0x000a, R10
+	MOVW $0x000b, R11
+	MOVW $0x000c, R12
+	MOVW $0x000d, R13
+	MOVW $0x000e, R14
+	MOVW $0x000f, R15
+	ADDW CX, AX
+	ADDW DX, AX
+	ADDW BX, AX
+	ADDW BP, AX
+	ADDW SI, AX
+	ADDW DI, AX
+	ADDW R8, AX
+	ADDW R9, AX
+	ADDW R10, AX
+	ADDW R11, AX
+	ADDW R12, AX
+	ADDW R13, AX
+	ADDW R14, AX
+	ADDW R15, AX
+	MOVW AX, ret+0(FP)
+	MOVW $0x0000, AX
+	MOVW $0x0000, CX
+	MOVW $0x0000, DX
+	MOVW $0x0000, BX
+	MOVW $0x0000, BP
+	MOVW $0x0000, SI
+	MOVW $0x0000, DI
+	MOVW $0x0000, R8
+	MOVW $0x0000, R9
+	MOVW $0x0000, R10
+	MOVW $0x0000, R11
+	MOVW $0x0000, R12
+	MOVW $0x0000, R13
+	MOVW $0x0000, R14
+	MOVW $0x0000, R15
+	ADDQ CX, AX
+	ADDQ DX, AX
+	ADDQ BX, AX
+	ADDQ BP, AX
+	ADDQ SI, AX
+	ADDQ DI, AX
+	ADDQ R8, AX
+	ADDQ R9, AX
+	ADDQ R10, AX
+	ADDQ R11, AX
+	ADDQ R12, AX
+	ADDQ R13, AX
+	ADDQ R14, AX
+	ADDQ R15, AX
+	SHRQ $0x10, AX
+	MOVQ AX, ret1+8(FP)
+	RET

tests/alloc/masks/masks_test.go

@@ -0,0 +1,15 @@
+package masks
+
+import (
+	"testing"
+)
+
+//go:generate go run asm.go -out masks.s -stubs stub.go
+
+func TestMasks(t *testing.T) {
+	const n = 15
+	const expect = n * (n + 1) / 2
+	if got16, got64 := Masks(); got16 != expect || got64 != expect {
+		t.Fatalf("Masks() = %v, %v; expect %v, %v", got16, got64, expect, expect)
+	}
+}

tests/alloc/masks/stub.go

@@ -0,0 +1,6 @@
+// Code generated by command: go run asm.go -out masks.s -stubs stub.go. DO NOT EDIT.
+
+package masks
+
+// Masks computes the sum 1+2+...+15 in two ways.
+func Masks() (uint16, uint64)