reg,pass: refactor allocation of aliased registers (#121)
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
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Michael McLoughlin
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GitHub
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66
tests/alloc/upper32/asm.go
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66
tests/alloc/upper32/asm.go
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// +build ignore
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package main
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import (
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"strconv"
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. "github.com/mmcloughlin/avo/build"
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. "github.com/mmcloughlin/avo/operand"
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. "github.com/mmcloughlin/avo/reg"
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)
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// The goal is to test for correct handling of 32-bit operands in 64-bit mode,
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// specifically that writes are zero-extended to 64 bits. This test is
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// constructed such that the register allocator would fail if this feature is
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// not accounted for. It consists of multiple copies of a 32-bit write followed
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// by a 64-bit read of the same register. Without special treatment liveness
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// analysis would consider the upper 32 bits to still be live prior to the
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// write. Therefore if we stack up enough copies of this, we could cause the
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// register allocator to fail.
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func main() {
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const (
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r = 14 // number of registers
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m = 3 // number of iterations
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n = r * m
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)
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TEXT("Upper32", NOSPLIT, "func() uint64")
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Doc("Upper32 computes the sum 1+2+...+" + strconv.Itoa(n) + ".")
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Comment("Initialize sum.")
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s := GP64()
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XORQ(s, s)
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// Allocate n 64-bit registers and populate them.
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Comment("Initialize registers.")
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x := make([]GPVirtual, n)
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for i := 0; i < n; i++ {
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x[i] = GP64()
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MOVQ(U64(0x9e77d78aacb8cbcc), x[i])
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}
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k := 0
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for i := 0; i < m; i++ {
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Commentf("Iteration %d.", i+1)
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// Write to the 32-bit aliases of r registers.
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for j := 0; j < r; j++ {
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MOVL(U32(k+j+1), x[k+j].As32())
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}
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// Sum them up.
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for j := 0; j < r; j++ {
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ADDQ(x[k+j], s)
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}
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k += r
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}
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Comment("Store result and return.")
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Store(s, ReturnIndex(0))
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RET()
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Generate()
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}
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2
tests/alloc/upper32/doc.go
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2
tests/alloc/upper32/doc.go
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// Package upper32 tests liveness analysis of 32-bit operations on 64-bit registers.
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package upper32
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6
tests/alloc/upper32/stub.go
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6
tests/alloc/upper32/stub.go
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// Code generated by command: go run asm.go -out upper32.s -stubs stub.go. DO NOT EDIT.
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package upper32
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// Upper32 computes the sum 1+2+...+42.
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func Upper32() uint64
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146
tests/alloc/upper32/upper32.s
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146
tests/alloc/upper32/upper32.s
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// Code generated by command: go run asm.go -out upper32.s -stubs stub.go. DO NOT EDIT.
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#include "textflag.h"
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// func Upper32() uint64
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TEXT ·Upper32(SB), NOSPLIT, $0-8
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// Initialize sum.
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XORQ AX, AX
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// Initialize registers.
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MOVQ $0x9e77d78aacb8cbcc, CX
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MOVQ $0x9e77d78aacb8cbcc, DX
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MOVQ $0x9e77d78aacb8cbcc, BX
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MOVQ $0x9e77d78aacb8cbcc, BP
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MOVQ $0x9e77d78aacb8cbcc, SI
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MOVQ $0x9e77d78aacb8cbcc, DI
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MOVQ $0x9e77d78aacb8cbcc, R8
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MOVQ $0x9e77d78aacb8cbcc, R9
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MOVQ $0x9e77d78aacb8cbcc, R10
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MOVQ $0x9e77d78aacb8cbcc, R11
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MOVQ $0x9e77d78aacb8cbcc, R12
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MOVQ $0x9e77d78aacb8cbcc, R13
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MOVQ $0x9e77d78aacb8cbcc, R14
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MOVQ $0x9e77d78aacb8cbcc, R15
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MOVQ $0x9e77d78aacb8cbcc, CX
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MOVQ $0x9e77d78aacb8cbcc, DX
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MOVQ $0x9e77d78aacb8cbcc, BX
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MOVQ $0x9e77d78aacb8cbcc, BP
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MOVQ $0x9e77d78aacb8cbcc, SI
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MOVQ $0x9e77d78aacb8cbcc, DI
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MOVQ $0x9e77d78aacb8cbcc, R8
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MOVQ $0x9e77d78aacb8cbcc, R9
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MOVQ $0x9e77d78aacb8cbcc, R10
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MOVQ $0x9e77d78aacb8cbcc, R11
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MOVQ $0x9e77d78aacb8cbcc, R12
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MOVQ $0x9e77d78aacb8cbcc, R13
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MOVQ $0x9e77d78aacb8cbcc, R14
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MOVQ $0x9e77d78aacb8cbcc, R15
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MOVQ $0x9e77d78aacb8cbcc, CX
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MOVQ $0x9e77d78aacb8cbcc, DX
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MOVQ $0x9e77d78aacb8cbcc, BX
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MOVQ $0x9e77d78aacb8cbcc, BP
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MOVQ $0x9e77d78aacb8cbcc, SI
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MOVQ $0x9e77d78aacb8cbcc, DI
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MOVQ $0x9e77d78aacb8cbcc, R8
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MOVQ $0x9e77d78aacb8cbcc, R9
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MOVQ $0x9e77d78aacb8cbcc, R10
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MOVQ $0x9e77d78aacb8cbcc, R11
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MOVQ $0x9e77d78aacb8cbcc, R12
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MOVQ $0x9e77d78aacb8cbcc, R13
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MOVQ $0x9e77d78aacb8cbcc, R14
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MOVQ $0x9e77d78aacb8cbcc, R15
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// Iteration 1.
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MOVL $0x00000001, CX
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MOVL $0x00000002, DX
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MOVL $0x00000003, BX
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MOVL $0x00000004, BP
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MOVL $0x00000005, SI
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MOVL $0x00000006, DI
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MOVL $0x00000007, R8
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MOVL $0x00000008, R9
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MOVL $0x00000009, R10
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MOVL $0x0000000a, R11
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MOVL $0x0000000b, R12
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MOVL $0x0000000c, R13
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MOVL $0x0000000d, R14
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MOVL $0x0000000e, R15
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ADDQ CX, AX
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ADDQ DX, AX
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ADDQ BX, AX
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ADDQ BP, AX
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ADDQ SI, AX
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ADDQ DI, AX
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ADDQ R8, AX
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ADDQ R9, AX
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ADDQ R10, AX
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ADDQ R11, AX
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ADDQ R12, AX
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ADDQ R13, AX
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ADDQ R14, AX
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ADDQ R15, AX
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// Iteration 2.
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MOVL $0x0000000f, CX
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MOVL $0x00000010, DX
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MOVL $0x00000011, BX
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MOVL $0x00000012, BP
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MOVL $0x00000013, SI
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MOVL $0x00000014, DI
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MOVL $0x00000015, R8
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MOVL $0x00000016, R9
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MOVL $0x00000017, R10
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MOVL $0x00000018, R11
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MOVL $0x00000019, R12
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MOVL $0x0000001a, R13
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MOVL $0x0000001b, R14
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MOVL $0x0000001c, R15
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ADDQ CX, AX
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ADDQ DX, AX
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ADDQ BX, AX
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ADDQ BP, AX
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ADDQ SI, AX
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ADDQ DI, AX
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ADDQ R8, AX
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ADDQ R9, AX
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ADDQ R10, AX
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ADDQ R11, AX
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ADDQ R12, AX
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ADDQ R13, AX
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ADDQ R14, AX
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ADDQ R15, AX
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// Iteration 3.
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MOVL $0x0000001d, CX
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MOVL $0x0000001e, DX
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MOVL $0x0000001f, BX
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MOVL $0x00000020, BP
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MOVL $0x00000021, SI
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MOVL $0x00000022, DI
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MOVL $0x00000023, R8
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MOVL $0x00000024, R9
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MOVL $0x00000025, R10
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MOVL $0x00000026, R11
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MOVL $0x00000027, R12
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MOVL $0x00000028, R13
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MOVL $0x00000029, R14
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MOVL $0x0000002a, R15
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ADDQ CX, AX
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ADDQ DX, AX
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ADDQ BX, AX
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ADDQ BP, AX
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ADDQ SI, AX
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ADDQ DI, AX
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ADDQ R8, AX
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ADDQ R9, AX
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ADDQ R10, AX
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ADDQ R11, AX
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ADDQ R12, AX
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ADDQ R13, AX
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ADDQ R14, AX
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ADDQ R15, AX
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// Store result and return.
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MOVQ AX, ret+0(FP)
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RET
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15
tests/alloc/upper32/upper32_test.go
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15
tests/alloc/upper32/upper32_test.go
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package upper32
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import (
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"testing"
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)
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//go:generate go run asm.go -out upper32.s -stubs stub.go
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func TestUpper32(t *testing.T) {
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const n = 14 * 3
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const expect = n * (n + 1) / 2
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if got := Upper32(); got != expect {
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t.Fatalf("Upper32() = %v; expect %v", got, expect)
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}
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}
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