reg,pass: refactor allocation of aliased registers (#121)
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
This commit is contained in:
Michael McLoughlin
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GitHub
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126469f13d
commit
f40d602170
22
tests/fixedbugs/issue100/asm.go
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22
tests/fixedbugs/issue100/asm.go
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// +build ignore
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package main
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import (
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. "github.com/mmcloughlin/avo/build"
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. "github.com/mmcloughlin/avo/operand"
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)
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func main() {
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TEXT("Issue100", NOSPLIT, "func() uint64")
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x := GP64()
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XORQ(x, x)
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for i := 1; i <= 100; i++ {
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t := GP64()
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MOVQ(U32(i), t)
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ADDQ(t.As64(), x)
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}
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Store(x, ReturnIndex(0))
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RET()
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Generate()
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}
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2
tests/fixedbugs/issue100/doc.go
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2
tests/fixedbugs/issue100/doc.go
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// Package issue100 contains a reproducer for a bug in aliased register allocation.
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package issue100
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209
tests/fixedbugs/issue100/issue100.s
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209
tests/fixedbugs/issue100/issue100.s
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// Code generated by command: go run asm.go -out issue100.s -stubs stub.go. DO NOT EDIT.
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#include "textflag.h"
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// func Issue100() uint64
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TEXT ·Issue100(SB), NOSPLIT, $0-8
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XORQ AX, AX
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MOVQ $0x00000001, CX
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ADDQ CX, AX
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MOVQ $0x00000002, CX
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ADDQ CX, AX
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MOVQ $0x00000003, CX
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ADDQ CX, AX
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MOVQ $0x00000004, CX
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ADDQ CX, AX
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MOVQ $0x00000005, CX
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ADDQ CX, AX
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MOVQ $0x00000006, CX
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ADDQ CX, AX
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MOVQ $0x00000007, CX
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ADDQ CX, AX
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MOVQ $0x00000008, CX
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ADDQ CX, AX
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MOVQ $0x00000009, CX
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ADDQ CX, AX
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MOVQ $0x0000000a, CX
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ADDQ CX, AX
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MOVQ $0x0000000b, CX
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ADDQ CX, AX
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MOVQ $0x0000000c, CX
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ADDQ CX, AX
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MOVQ $0x0000000d, CX
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ADDQ CX, AX
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MOVQ $0x0000000e, CX
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ADDQ CX, AX
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MOVQ $0x0000000f, CX
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ADDQ CX, AX
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MOVQ $0x00000010, CX
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ADDQ CX, AX
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MOVQ $0x00000011, CX
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ADDQ CX, AX
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MOVQ $0x00000012, CX
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ADDQ CX, AX
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MOVQ $0x00000013, CX
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ADDQ CX, AX
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MOVQ $0x00000014, CX
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ADDQ CX, AX
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MOVQ $0x00000015, CX
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ADDQ CX, AX
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MOVQ $0x00000016, CX
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ADDQ CX, AX
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MOVQ $0x00000017, CX
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ADDQ CX, AX
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MOVQ $0x00000018, CX
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ADDQ CX, AX
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MOVQ $0x00000019, CX
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ADDQ CX, AX
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MOVQ $0x0000001a, CX
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ADDQ CX, AX
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MOVQ $0x0000001b, CX
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ADDQ CX, AX
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MOVQ $0x0000001c, CX
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ADDQ CX, AX
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MOVQ $0x0000001d, CX
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ADDQ CX, AX
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MOVQ $0x0000001e, CX
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ADDQ CX, AX
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MOVQ $0x0000001f, CX
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ADDQ CX, AX
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MOVQ $0x00000020, CX
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ADDQ CX, AX
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MOVQ $0x00000021, CX
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ADDQ CX, AX
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MOVQ $0x00000022, CX
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ADDQ CX, AX
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MOVQ $0x00000023, CX
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ADDQ CX, AX
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MOVQ $0x00000024, CX
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ADDQ CX, AX
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MOVQ $0x00000025, CX
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ADDQ CX, AX
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MOVQ $0x00000026, CX
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ADDQ CX, AX
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MOVQ $0x00000027, CX
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ADDQ CX, AX
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MOVQ $0x00000028, CX
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ADDQ CX, AX
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MOVQ $0x00000029, CX
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ADDQ CX, AX
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MOVQ $0x0000002a, CX
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ADDQ CX, AX
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MOVQ $0x0000002b, CX
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ADDQ CX, AX
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MOVQ $0x0000002c, CX
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ADDQ CX, AX
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MOVQ $0x0000002d, CX
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ADDQ CX, AX
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MOVQ $0x0000002e, CX
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ADDQ CX, AX
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MOVQ $0x0000002f, CX
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ADDQ CX, AX
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MOVQ $0x00000030, CX
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ADDQ CX, AX
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MOVQ $0x00000031, CX
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ADDQ CX, AX
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MOVQ $0x00000032, CX
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ADDQ CX, AX
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MOVQ $0x00000033, CX
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ADDQ CX, AX
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MOVQ $0x00000034, CX
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ADDQ CX, AX
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MOVQ $0x00000035, CX
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ADDQ CX, AX
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MOVQ $0x00000036, CX
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ADDQ CX, AX
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MOVQ $0x00000037, CX
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ADDQ CX, AX
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MOVQ $0x00000038, CX
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ADDQ CX, AX
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MOVQ $0x00000039, CX
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ADDQ CX, AX
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MOVQ $0x0000003a, CX
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ADDQ CX, AX
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MOVQ $0x0000003b, CX
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ADDQ CX, AX
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MOVQ $0x0000003c, CX
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ADDQ CX, AX
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MOVQ $0x0000003d, CX
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ADDQ CX, AX
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MOVQ $0x0000003e, CX
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ADDQ CX, AX
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MOVQ $0x0000003f, CX
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ADDQ CX, AX
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MOVQ $0x00000040, CX
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ADDQ CX, AX
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MOVQ $0x00000041, CX
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ADDQ CX, AX
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MOVQ $0x00000042, CX
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ADDQ CX, AX
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MOVQ $0x00000043, CX
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ADDQ CX, AX
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MOVQ $0x00000044, CX
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ADDQ CX, AX
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MOVQ $0x00000045, CX
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ADDQ CX, AX
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MOVQ $0x00000046, CX
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ADDQ CX, AX
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MOVQ $0x00000047, CX
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ADDQ CX, AX
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MOVQ $0x00000048, CX
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ADDQ CX, AX
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MOVQ $0x00000049, CX
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ADDQ CX, AX
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MOVQ $0x0000004a, CX
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ADDQ CX, AX
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MOVQ $0x0000004b, CX
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ADDQ CX, AX
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MOVQ $0x0000004c, CX
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ADDQ CX, AX
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MOVQ $0x0000004d, CX
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ADDQ CX, AX
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MOVQ $0x0000004e, CX
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ADDQ CX, AX
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MOVQ $0x0000004f, CX
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ADDQ CX, AX
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MOVQ $0x00000050, CX
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ADDQ CX, AX
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MOVQ $0x00000051, CX
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ADDQ CX, AX
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MOVQ $0x00000052, CX
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ADDQ CX, AX
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MOVQ $0x00000053, CX
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ADDQ CX, AX
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MOVQ $0x00000054, CX
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ADDQ CX, AX
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MOVQ $0x00000055, CX
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ADDQ CX, AX
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MOVQ $0x00000056, CX
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ADDQ CX, AX
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MOVQ $0x00000057, CX
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ADDQ CX, AX
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MOVQ $0x00000058, CX
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ADDQ CX, AX
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MOVQ $0x00000059, CX
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ADDQ CX, AX
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MOVQ $0x0000005a, CX
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ADDQ CX, AX
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MOVQ $0x0000005b, CX
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ADDQ CX, AX
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MOVQ $0x0000005c, CX
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ADDQ CX, AX
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MOVQ $0x0000005d, CX
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ADDQ CX, AX
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MOVQ $0x0000005e, CX
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ADDQ CX, AX
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MOVQ $0x0000005f, CX
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ADDQ CX, AX
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MOVQ $0x00000060, CX
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ADDQ CX, AX
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MOVQ $0x00000061, CX
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ADDQ CX, AX
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MOVQ $0x00000062, CX
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ADDQ CX, AX
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MOVQ $0x00000063, CX
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ADDQ CX, AX
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MOVQ $0x00000064, CX
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ADDQ CX, AX
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MOVQ AX, ret+0(FP)
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RET
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15
tests/fixedbugs/issue100/issue100_test.go
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15
tests/fixedbugs/issue100/issue100_test.go
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package issue100
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import (
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"testing"
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)
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//go:generate go run asm.go -out issue100.s -stubs stub.go
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func TestIssue100(t *testing.T) {
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n := uint64(100)
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expect := n * (n + 1) / 2
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if got := Issue100(); got != expect {
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t.Fatalf("Issue100() = %v; expect %v", got, expect)
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}
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}
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5
tests/fixedbugs/issue100/stub.go
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5
tests/fixedbugs/issue100/stub.go
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@@ -0,0 +1,5 @@
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// Code generated by command: go run asm.go -out issue100.s -stubs stub.go. DO NOT EDIT.
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package issue100
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func Issue100() uint64
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23
tests/fixedbugs/issue65/castphysical.go
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23
tests/fixedbugs/issue65/castphysical.go
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// +build generate
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//go:generate go run $GOFILE
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// Regression test for a bug where casting a physical register would give the
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// error "non physical register found".
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//
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// See: https://github.com/mmcloughlin/avo/issues/65#issuecomment-576850145
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package main
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import (
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. "github.com/mmcloughlin/avo/build"
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. "github.com/mmcloughlin/avo/operand"
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. "github.com/mmcloughlin/avo/reg"
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)
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func main() {
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TEXT("Issue65", NOSPLIT, "func()")
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VINSERTI128(Imm(1), Y0.AsX(), Y1, Y2)
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RET()
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Generate()
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}
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