diff --git a/ast.go b/ast.go
index cba96bb..6fb60fc 100644
--- a/ast.go
+++ b/ast.go
@@ -10,15 +10,6 @@ type Asm interface {
 	Asm() string
 }
 
-// GoType represents a Golang type.
-type GoType interface{}
-
-// Parameter represents a parameter to an assembly function.
-type Parameter struct {
-	Name string
-	Type GoType
-}
-
 type Operand interface {
 	Asm
 }
@@ -112,6 +103,7 @@ func NewFile() *File {
 type Function struct {
 	Name      string
 	Signature *gotypes.Signature
+	LocalSize int
 
 	Nodes []Node
 
@@ -133,6 +125,12 @@ func (f *Function) SetSignature(s *gotypes.Signature) {
 	f.Signature = s
 }
 
+func (f *Function) AllocLocal(size int) operand.Mem {
+	ptr := operand.NewStackAddr(f.LocalSize)
+	f.LocalSize += size
+	return ptr
+}
+
 func (f *Function) AddInstruction(i *Instruction) {
 	f.AddNode(i)
 }
@@ -164,8 +162,7 @@ func (f *Function) Stub() string {
 
 // FrameBytes returns the size of the stack frame in bytes.
 func (f *Function) FrameBytes() int {
-	// TODO(mbm): implement Function.FrameBytes()
-	return 0
+	return f.LocalSize
 }
 
 // ArgumentBytes returns the size of the arguments in bytes.
diff --git a/build/context.go b/build/context.go
index 3dbdbf4..4891376 100644
--- a/build/context.go
+++ b/build/context.go
@@ -6,6 +6,7 @@ import (
 
 	"github.com/mmcloughlin/avo"
 	"github.com/mmcloughlin/avo/gotypes"
+	"github.com/mmcloughlin/avo/operand"
 	"github.com/mmcloughlin/avo/reg"
 	"golang.org/x/tools/go/packages"
 )
@@ -69,6 +70,10 @@ func (c *Context) types() *types.Package {
 	return c.pkg.Types
 }
 
+func (c *Context) AllocLocal(size int) operand.Mem {
+	return c.activefunc().AllocLocal(size)
+}
+
 func (c *Context) Instruction(i *avo.Instruction) {
 	c.activefunc().AddNode(i)
 }
diff --git a/build/global.go b/build/global.go
index f89fe28..5251d95 100644
--- a/build/global.go
+++ b/build/global.go
@@ -5,6 +5,7 @@ import (
 	"os"
 
 	"github.com/mmcloughlin/avo/gotypes"
+	"github.com/mmcloughlin/avo/operand"
 
 	"github.com/mmcloughlin/avo/reg"
 
@@ -47,3 +48,5 @@ func ReturnIndex(i int) gotypes.Component  { return ctx.ReturnIndex(i) }
 
 func Load(src gotypes.Component, dst reg.Register) reg.Register { return ctx.Load(src, dst) }
 func Store(src reg.Register, dst gotypes.Component)             { ctx.Store(src, dst) }
+
+func AllocLocal(size int) operand.Mem { return ctx.AllocLocal(size) }
diff --git a/examples/sha1/asm.go b/examples/sha1/asm.go
new file mode 100644
index 0000000..8888ad0
--- /dev/null
+++ b/examples/sha1/asm.go
@@ -0,0 +1,124 @@
+// +build ignore
+
+package main
+
+import (
+	. "github.com/mmcloughlin/avo/build"
+	. "github.com/mmcloughlin/avo/operand"
+	"github.com/mmcloughlin/avo/reg"
+)
+
+func main() {
+	TEXT("block", "func(h *[5]uint32, m []byte)")
+	h := Mem{Base: Load(Param("h"), GP64v())}
+	m := Mem{Base: Load(Param("m").Base(), GP64v())}
+
+	// Store message values on the stack.
+	w := AllocLocal(64)
+	W := func(r int) Mem { return w.Idx((r % 16) * 4) }
+
+	// Load initial hash.
+	h0, h1, h2, h3, h4 := GP32v(), GP32v(), GP32v(), GP32v(), GP32v()
+
+	MOVL(h.Idx(0), h0)
+	MOVL(h.Idx(4), h1)
+	MOVL(h.Idx(8), h2)
+	MOVL(h.Idx(12), h3)
+	MOVL(h.Idx(16), h4)
+
+	// Initialize registers.
+	a, b, c, d, e := GP32v(), GP32v(), GP32v(), GP32v(), GP32v()
+
+	MOVL(h0, a)
+	MOVL(h1, b)
+	MOVL(h2, c)
+	MOVL(h3, d)
+	MOVL(h4, e)
+
+	// Generate round updates.
+	quarter := []struct {
+		F func(reg.Register, reg.Register, reg.Register) reg.Register
+		K uint32
+	}{
+		{choose, 0x5a827999},
+		{xor, 0x6ed9eba1},
+		{majority, 0x8f1bbcdc},
+		{xor, 0xca62c1d6},
+	}
+
+	for r := 0; r < 80; r++ {
+		q := quarter[r/20]
+
+		// Load message value.
+		u := GP32v()
+		if r < 16 {
+			MOVL(m.Idx(4*r), u)
+			BSWAPL(u)
+		} else {
+			MOVL(W(r-3), u)
+			XORL(W(r-8), u)
+			XORL(W(r-14), u)
+			XORL(W(r-16), u)
+			ROLL(Imm(1), u)
+		}
+		MOVL(u, W(r))
+
+		// Compute the next state register.
+		t := GP32v()
+		MOVL(a, t)
+		ROLL(Imm(5), t)
+		ADDL(q.F(b, c, d), t)
+		ADDL(e, t)
+		ADDL(Imm(q.K), t)
+		ADDL(u, t)
+
+		// Update registers.
+		ROLL(Imm(30), b)
+		a, b, c, d, e = t, a, b, c, d
+	}
+
+	// Final add.
+	ADDL(a, h0)
+	ADDL(b, h1)
+	ADDL(c, h2)
+	ADDL(d, h3)
+	ADDL(e, h4)
+
+	// Store results back.
+	MOVL(h0, h.Idx(0))
+	MOVL(h1, h.Idx(4))
+	MOVL(h2, h.Idx(8))
+	MOVL(h3, h.Idx(12))
+	MOVL(h4, h.Idx(16))
+	RET()
+
+	Generate()
+}
+
+func choose(b, c, d reg.Register) reg.Register {
+	r := GP32v()
+	MOVL(d, r)
+	XORL(c, r)
+	ANDL(b, r)
+	XORL(d, r)
+	return r
+}
+
+func xor(b, c, d reg.Register) reg.Register {
+	r := GP32v()
+	MOVL(b, r)
+	XORL(c, r)
+	XORL(d, r)
+	return r
+}
+
+func majority(b, c, d reg.Register) reg.Register {
+	t, r := GP32v(), GP32v()
+	MOVL(b, t)
+	ORL(c, t)
+	ANDL(d, t)
+	MOVL(b, r)
+	ANDL(c, r)
+	ORL(t, r)
+	return r
+}
diff --git a/examples/sha1/sha1.s b/examples/sha1/sha1.s
new file mode 100644
index 0000000..5d65534
--- /dev/null
+++ b/examples/sha1/sha1.s
@@ -0,0 +1,1341 @@
+// Code generated by command: go run asm.go -out sha1.s -stubs stub.go. DO NOT EDIT.
+
+#include "textflag.h"
+
+// func block(h *[5]uint32, m []byte)
+TEXT ·block(SB),0,$64-32
+	MOVQ	h(FP), AX
+	MOVQ	m_base+8(FP), CX
+	MOVL	(AX), DX
+	MOVL	4(AX), BX
+	MOVL	8(AX), BP
+	MOVL	12(AX), SI
+	MOVL	16(AX), DI
+	MOVL	DX, R8
+	MOVL	BX, R9
+	MOVL	BP, R10
+	MOVL	SI, R11
+	MOVL	DI, R12
+	MOVL	(CX), R13
+	BSWAPL	R13
+	MOVL	R13, (SP)
+	MOVL	R8, R14
+	ROLL	$0x5, R14
+	MOVL	R11, R15
+	XORL	R10, R15
+	ANDL	R9, R15
+	XORL	R11, R15
+	ADDL	R15, R14
+	ADDL	R12, R14
+	ADDL	$0x5a827999, R14
+	ADDL	R13, R14
+	ROLL	$0x1e, R9
+	MOVL	4(CX), R12
+	BSWAPL	R12
+	MOVL	R12, 4(SP)
+	MOVL	R14, R13
+	ROLL	$0x5, R13
+	MOVL	R10, R15
+	XORL	R9, R15
+	ANDL	R8, R15
+	XORL	R10, R15
+	ADDL	R15, R13
+	ADDL	R11, R13
+	ADDL	$0x5a827999, R13
+	ADDL	R12, R13
+	ROLL	$0x1e, R8
+	MOVL	8(CX), R11
+	BSWAPL	R11
+	MOVL	R11, 8(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R9, R15
+	XORL	R8, R15
+	ANDL	R14, R15
+	XORL	R9, R15
+	ADDL	R15, R12
+	ADDL	R10, R12
+	ADDL	$0x5a827999, R12
+	ADDL	R11, R12
+	ROLL	$0x1e, R14
+	MOVL	12(CX), R10
+	BSWAPL	R10
+	MOVL	R10, 12(SP)
+	MOVL	R12, R11
+	ROLL	$0x5, R11
+	MOVL	R8, R15
+	XORL	R14, R15
+	ANDL	R13, R15
+	XORL	R8, R15
+	ADDL	R15, R11
+	ADDL	R9, R11
+	ADDL	$0x5a827999, R11
+	ADDL	R10, R11
+	ROLL	$0x1e, R13
+	MOVL	16(CX), R9
+	BSWAPL	R9
+	MOVL	R9, 16(SP)
+	MOVL	R11, R10
+	ROLL	$0x5, R10
+	MOVL	R14, R15
+	XORL	R13, R15
+	ANDL	R12, R15
+	XORL	R14, R15
+	ADDL	R15, R10
+	ADDL	R8, R10
+	ADDL	$0x5a827999, R10
+	ADDL	R9, R10
+	ROLL	$0x1e, R12
+	MOVL	20(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 20(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R13, R15
+	XORL	R12, R15
+	ANDL	R11, R15
+	XORL	R13, R15
+	ADDL	R15, R9
+	ADDL	R14, R9
+	ADDL	$0x5a827999, R9
+	ADDL	R8, R9
+	ROLL	$0x1e, R11
+	MOVL	24(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 24(SP)
+	MOVL	R9, R14
+	ROLL	$0x5, R14
+	MOVL	R12, R15
+	XORL	R11, R15
+	ANDL	R10, R15
+	XORL	R12, R15
+	ADDL	R15, R14
+	ADDL	R13, R14
+	ADDL	$0x5a827999, R14
+	ADDL	R8, R14
+	ROLL	$0x1e, R10
+	MOVL	28(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 28(SP)
+	MOVL	R14, R13
+	ROLL	$0x5, R13
+	MOVL	R11, R15
+	XORL	R10, R15
+	ANDL	R9, R15
+	XORL	R11, R15
+	ADDL	R15, R13
+	ADDL	R12, R13
+	ADDL	$0x5a827999, R13
+	ADDL	R8, R13
+	ROLL	$0x1e, R9
+	MOVL	32(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 32(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R10, R15
+	XORL	R9, R15
+	ANDL	R14, R15
+	XORL	R10, R15
+	ADDL	R15, R12
+	ADDL	R11, R12
+	ADDL	$0x5a827999, R12
+	ADDL	R8, R12
+	ROLL	$0x1e, R14
+	MOVL	36(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 36(SP)
+	MOVL	R12, R11
+	ROLL	$0x5, R11
+	MOVL	R9, R15
+	XORL	R14, R15
+	ANDL	R13, R15
+	XORL	R9, R15
+	ADDL	R15, R11
+	ADDL	R10, R11
+	ADDL	$0x5a827999, R11
+	ADDL	R8, R11
+	ROLL	$0x1e, R13
+	MOVL	40(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 40(SP)
+	MOVL	R11, R10
+	ROLL	$0x5, R10
+	MOVL	R14, R15
+	XORL	R13, R15
+	ANDL	R12, R15
+	XORL	R14, R15
+	ADDL	R15, R10
+	ADDL	R9, R10
+	ADDL	$0x5a827999, R10
+	ADDL	R8, R10
+	ROLL	$0x1e, R12
+	MOVL	44(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 44(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R13, R15
+	XORL	R12, R15
+	ANDL	R11, R15
+	XORL	R13, R15
+	ADDL	R15, R9
+	ADDL	R14, R9
+	ADDL	$0x5a827999, R9
+	ADDL	R8, R9
+	ROLL	$0x1e, R11
+	MOVL	48(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 48(SP)
+	MOVL	R9, R14
+	ROLL	$0x5, R14
+	MOVL	R12, R15
+	XORL	R11, R15
+	ANDL	R10, R15
+	XORL	R12, R15
+	ADDL	R15, R14
+	ADDL	R13, R14
+	ADDL	$0x5a827999, R14
+	ADDL	R8, R14
+	ROLL	$0x1e, R10
+	MOVL	52(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 52(SP)
+	MOVL	R14, R13
+	ROLL	$0x5, R13
+	MOVL	R11, R15
+	XORL	R10, R15
+	ANDL	R9, R15
+	XORL	R11, R15
+	ADDL	R15, R13
+	ADDL	R12, R13
+	ADDL	$0x5a827999, R13
+	ADDL	R8, R13
+	ROLL	$0x1e, R9
+	MOVL	56(CX), R8
+	BSWAPL	R8
+	MOVL	R8, 56(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R10, R15
+	XORL	R9, R15
+	ANDL	R14, R15
+	XORL	R10, R15
+	ADDL	R15, R12
+	ADDL	R11, R12
+	ADDL	$0x5a827999, R12
+	ADDL	R8, R12
+	ROLL	$0x1e, R14
+	MOVL	60(CX), CX
+	BSWAPL	CX
+	MOVL	CX, 60(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R9, R11
+	XORL	R14, R11
+	ANDL	R13, R11
+	XORL	R9, R11
+	ADDL	R11, R8
+	ADDL	R10, R8
+	ADDL	$0x5a827999, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	52(SP), CX
+	XORL	32(SP), CX
+	XORL	8(SP), CX
+	XORL	(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, (SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R14, R11
+	XORL	R13, R11
+	ANDL	R12, R11
+	XORL	R14, R11
+	ADDL	R11, R10
+	ADDL	R9, R10
+	ADDL	$0x5a827999, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	56(SP), CX
+	XORL	36(SP), CX
+	XORL	12(SP), CX
+	XORL	4(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 4(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R13, R11
+	XORL	R12, R11
+	ANDL	R8, R11
+	XORL	R13, R11
+	ADDL	R11, R9
+	ADDL	R14, R9
+	ADDL	$0x5a827999, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	60(SP), CX
+	XORL	40(SP), CX
+	XORL	16(SP), CX
+	XORL	8(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 8(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R12, R14
+	XORL	R8, R14
+	ANDL	R10, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0x5a827999, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	(SP), CX
+	XORL	44(SP), CX
+	XORL	20(SP), CX
+	XORL	12(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 12(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R8, R14
+	XORL	R10, R14
+	ANDL	R9, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0x5a827999, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	4(SP), CX
+	XORL	48(SP), CX
+	XORL	24(SP), CX
+	XORL	16(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 16(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0x6ed9eba1, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	8(SP), CX
+	XORL	52(SP), CX
+	XORL	28(SP), CX
+	XORL	20(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 20(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0x6ed9eba1, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	12(SP), CX
+	XORL	56(SP), CX
+	XORL	32(SP), CX
+	XORL	24(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 24(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	XORL	R13, R14
+	XORL	R11, R14
+	ADDL	R14, R10
+	ADDL	R9, R10
+	ADDL	$0x6ed9eba1, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	16(SP), CX
+	XORL	60(SP), CX
+	XORL	36(SP), CX
+	XORL	28(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 28(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	XORL	R12, R14
+	XORL	R13, R14
+	ADDL	R14, R9
+	ADDL	R11, R9
+	ADDL	$0x6ed9eba1, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	20(SP), CX
+	XORL	(SP), CX
+	XORL	40(SP), CX
+	XORL	32(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 32(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0x6ed9eba1, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	24(SP), CX
+	XORL	4(SP), CX
+	XORL	44(SP), CX
+	XORL	36(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 36(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0x6ed9eba1, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	28(SP), CX
+	XORL	8(SP), CX
+	XORL	48(SP), CX
+	XORL	40(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 40(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0x6ed9eba1, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	32(SP), CX
+	XORL	12(SP), CX
+	XORL	52(SP), CX
+	XORL	44(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 44(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0x6ed9eba1, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	36(SP), CX
+	XORL	16(SP), CX
+	XORL	56(SP), CX
+	XORL	48(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 48(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	XORL	R13, R14
+	XORL	R11, R14
+	ADDL	R14, R10
+	ADDL	R9, R10
+	ADDL	$0x6ed9eba1, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	40(SP), CX
+	XORL	20(SP), CX
+	XORL	60(SP), CX
+	XORL	52(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 52(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	XORL	R12, R14
+	XORL	R13, R14
+	ADDL	R14, R9
+	ADDL	R11, R9
+	ADDL	$0x6ed9eba1, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	44(SP), CX
+	XORL	24(SP), CX
+	XORL	(SP), CX
+	XORL	56(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 56(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0x6ed9eba1, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	48(SP), CX
+	XORL	28(SP), CX
+	XORL	4(SP), CX
+	XORL	60(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 60(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0x6ed9eba1, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	52(SP), CX
+	XORL	32(SP), CX
+	XORL	8(SP), CX
+	XORL	(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, (SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0x6ed9eba1, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	56(SP), CX
+	XORL	36(SP), CX
+	XORL	12(SP), CX
+	XORL	4(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 4(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0x6ed9eba1, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	60(SP), CX
+	XORL	40(SP), CX
+	XORL	16(SP), CX
+	XORL	8(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 8(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	XORL	R13, R14
+	XORL	R11, R14
+	ADDL	R14, R10
+	ADDL	R9, R10
+	ADDL	$0x6ed9eba1, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	(SP), CX
+	XORL	44(SP), CX
+	XORL	20(SP), CX
+	XORL	12(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 12(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	XORL	R12, R14
+	XORL	R13, R14
+	ADDL	R14, R9
+	ADDL	R11, R9
+	ADDL	$0x6ed9eba1, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	4(SP), CX
+	XORL	48(SP), CX
+	XORL	24(SP), CX
+	XORL	16(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 16(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0x6ed9eba1, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	8(SP), CX
+	XORL	52(SP), CX
+	XORL	28(SP), CX
+	XORL	20(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 20(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0x6ed9eba1, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	12(SP), CX
+	XORL	56(SP), CX
+	XORL	32(SP), CX
+	XORL	24(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 24(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0x6ed9eba1, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	16(SP), CX
+	XORL	60(SP), CX
+	XORL	36(SP), CX
+	XORL	28(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 28(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0x6ed9eba1, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	20(SP), CX
+	XORL	(SP), CX
+	XORL	40(SP), CX
+	XORL	32(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 32(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	ORL	R13, R14
+	ANDL	R11, R14
+	MOVL	R12, R15
+	ANDL	R13, R15
+	ORL	R14, R15
+	ADDL	R15, R10
+	ADDL	R9, R10
+	ADDL	$0x8f1bbcdc, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	24(SP), CX
+	XORL	4(SP), CX
+	XORL	44(SP), CX
+	XORL	36(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 36(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	ORL	R12, R14
+	ANDL	R13, R14
+	MOVL	R8, R15
+	ANDL	R12, R15
+	ORL	R14, R15
+	ADDL	R15, R9
+	ADDL	R11, R9
+	ADDL	$0x8f1bbcdc, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	28(SP), CX
+	XORL	8(SP), CX
+	XORL	48(SP), CX
+	XORL	40(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 40(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	ORL	R8, R14
+	ANDL	R12, R14
+	MOVL	R10, R15
+	ANDL	R8, R15
+	ORL	R14, R15
+	ADDL	R15, R11
+	ADDL	R13, R11
+	ADDL	$0x8f1bbcdc, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	32(SP), CX
+	XORL	12(SP), CX
+	XORL	52(SP), CX
+	XORL	44(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 44(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	ORL	R10, R14
+	ANDL	R8, R14
+	MOVL	R9, R15
+	ANDL	R10, R15
+	ORL	R14, R15
+	ADDL	R15, R13
+	ADDL	R12, R13
+	ADDL	$0x8f1bbcdc, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	36(SP), CX
+	XORL	16(SP), CX
+	XORL	56(SP), CX
+	XORL	48(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 48(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	ORL	R9, R14
+	ANDL	R10, R14
+	MOVL	R11, R15
+	ANDL	R9, R15
+	ORL	R14, R15
+	ADDL	R15, R12
+	ADDL	R8, R12
+	ADDL	$0x8f1bbcdc, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	40(SP), CX
+	XORL	20(SP), CX
+	XORL	60(SP), CX
+	XORL	52(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 52(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	ORL	R11, R14
+	ANDL	R9, R14
+	MOVL	R13, R15
+	ANDL	R11, R15
+	ORL	R14, R15
+	ADDL	R15, R8
+	ADDL	R10, R8
+	ADDL	$0x8f1bbcdc, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	44(SP), CX
+	XORL	24(SP), CX
+	XORL	(SP), CX
+	XORL	56(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 56(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	ORL	R13, R14
+	ANDL	R11, R14
+	MOVL	R12, R15
+	ANDL	R13, R15
+	ORL	R14, R15
+	ADDL	R15, R10
+	ADDL	R9, R10
+	ADDL	$0x8f1bbcdc, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	48(SP), CX
+	XORL	28(SP), CX
+	XORL	4(SP), CX
+	XORL	60(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 60(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	ORL	R12, R14
+	ANDL	R13, R14
+	MOVL	R8, R15
+	ANDL	R12, R15
+	ORL	R14, R15
+	ADDL	R15, R9
+	ADDL	R11, R9
+	ADDL	$0x8f1bbcdc, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	52(SP), CX
+	XORL	32(SP), CX
+	XORL	8(SP), CX
+	XORL	(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, (SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	ORL	R8, R14
+	ANDL	R12, R14
+	MOVL	R10, R15
+	ANDL	R8, R15
+	ORL	R14, R15
+	ADDL	R15, R11
+	ADDL	R13, R11
+	ADDL	$0x8f1bbcdc, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	56(SP), CX
+	XORL	36(SP), CX
+	XORL	12(SP), CX
+	XORL	4(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 4(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	ORL	R10, R14
+	ANDL	R8, R14
+	MOVL	R9, R15
+	ANDL	R10, R15
+	ORL	R14, R15
+	ADDL	R15, R13
+	ADDL	R12, R13
+	ADDL	$0x8f1bbcdc, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	60(SP), CX
+	XORL	40(SP), CX
+	XORL	16(SP), CX
+	XORL	8(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 8(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	ORL	R9, R14
+	ANDL	R10, R14
+	MOVL	R11, R15
+	ANDL	R9, R15
+	ORL	R14, R15
+	ADDL	R15, R12
+	ADDL	R8, R12
+	ADDL	$0x8f1bbcdc, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	(SP), CX
+	XORL	44(SP), CX
+	XORL	20(SP), CX
+	XORL	12(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 12(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	ORL	R11, R14
+	ANDL	R9, R14
+	MOVL	R13, R15
+	ANDL	R11, R15
+	ORL	R14, R15
+	ADDL	R15, R8
+	ADDL	R10, R8
+	ADDL	$0x8f1bbcdc, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	4(SP), CX
+	XORL	48(SP), CX
+	XORL	24(SP), CX
+	XORL	16(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 16(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	ORL	R13, R14
+	ANDL	R11, R14
+	MOVL	R12, R15
+	ANDL	R13, R15
+	ORL	R14, R15
+	ADDL	R15, R10
+	ADDL	R9, R10
+	ADDL	$0x8f1bbcdc, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	8(SP), CX
+	XORL	52(SP), CX
+	XORL	28(SP), CX
+	XORL	20(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 20(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	ORL	R12, R14
+	ANDL	R13, R14
+	MOVL	R8, R15
+	ANDL	R12, R15
+	ORL	R14, R15
+	ADDL	R15, R9
+	ADDL	R11, R9
+	ADDL	$0x8f1bbcdc, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	12(SP), CX
+	XORL	56(SP), CX
+	XORL	32(SP), CX
+	XORL	24(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 24(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	ORL	R8, R14
+	ANDL	R12, R14
+	MOVL	R10, R15
+	ANDL	R8, R15
+	ORL	R14, R15
+	ADDL	R15, R11
+	ADDL	R13, R11
+	ADDL	$0x8f1bbcdc, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	16(SP), CX
+	XORL	60(SP), CX
+	XORL	36(SP), CX
+	XORL	28(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 28(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	ORL	R10, R14
+	ANDL	R8, R14
+	MOVL	R9, R15
+	ANDL	R10, R15
+	ORL	R14, R15
+	ADDL	R15, R13
+	ADDL	R12, R13
+	ADDL	$0x8f1bbcdc, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	20(SP), CX
+	XORL	(SP), CX
+	XORL	40(SP), CX
+	XORL	32(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 32(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	ORL	R9, R14
+	ANDL	R10, R14
+	MOVL	R11, R15
+	ANDL	R9, R15
+	ORL	R14, R15
+	ADDL	R15, R12
+	ADDL	R8, R12
+	ADDL	$0x8f1bbcdc, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	24(SP), CX
+	XORL	4(SP), CX
+	XORL	44(SP), CX
+	XORL	36(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 36(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	ORL	R11, R14
+	ANDL	R9, R14
+	MOVL	R13, R15
+	ANDL	R11, R15
+	ORL	R14, R15
+	ADDL	R15, R8
+	ADDL	R10, R8
+	ADDL	$0x8f1bbcdc, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	28(SP), CX
+	XORL	8(SP), CX
+	XORL	48(SP), CX
+	XORL	40(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 40(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	ORL	R13, R14
+	ANDL	R11, R14
+	MOVL	R12, R15
+	ANDL	R13, R15
+	ORL	R14, R15
+	ADDL	R15, R10
+	ADDL	R9, R10
+	ADDL	$0x8f1bbcdc, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	32(SP), CX
+	XORL	12(SP), CX
+	XORL	52(SP), CX
+	XORL	44(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 44(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	ORL	R12, R14
+	ANDL	R13, R14
+	MOVL	R8, R15
+	ANDL	R12, R15
+	ORL	R14, R15
+	ADDL	R15, R9
+	ADDL	R11, R9
+	ADDL	$0x8f1bbcdc, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	36(SP), CX
+	XORL	16(SP), CX
+	XORL	56(SP), CX
+	XORL	48(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 48(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0xca62c1d6, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	40(SP), CX
+	XORL	20(SP), CX
+	XORL	60(SP), CX
+	XORL	52(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 52(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0xca62c1d6, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	44(SP), CX
+	XORL	24(SP), CX
+	XORL	(SP), CX
+	XORL	56(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 56(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0xca62c1d6, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	48(SP), CX
+	XORL	28(SP), CX
+	XORL	4(SP), CX
+	XORL	60(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 60(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0xca62c1d6, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	52(SP), CX
+	XORL	32(SP), CX
+	XORL	8(SP), CX
+	XORL	(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, (SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	XORL	R13, R14
+	XORL	R11, R14
+	ADDL	R14, R10
+	ADDL	R9, R10
+	ADDL	$0xca62c1d6, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	56(SP), CX
+	XORL	36(SP), CX
+	XORL	12(SP), CX
+	XORL	4(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 4(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	XORL	R12, R14
+	XORL	R13, R14
+	ADDL	R14, R9
+	ADDL	R11, R9
+	ADDL	$0xca62c1d6, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	60(SP), CX
+	XORL	40(SP), CX
+	XORL	16(SP), CX
+	XORL	8(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 8(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0xca62c1d6, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	(SP), CX
+	XORL	44(SP), CX
+	XORL	20(SP), CX
+	XORL	12(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 12(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0xca62c1d6, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	4(SP), CX
+	XORL	48(SP), CX
+	XORL	24(SP), CX
+	XORL	16(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 16(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0xca62c1d6, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	8(SP), CX
+	XORL	52(SP), CX
+	XORL	28(SP), CX
+	XORL	20(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 20(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0xca62c1d6, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	12(SP), CX
+	XORL	56(SP), CX
+	XORL	32(SP), CX
+	XORL	24(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 24(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	XORL	R13, R14
+	XORL	R11, R14
+	ADDL	R14, R10
+	ADDL	R9, R10
+	ADDL	$0xca62c1d6, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	16(SP), CX
+	XORL	60(SP), CX
+	XORL	36(SP), CX
+	XORL	28(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 28(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	XORL	R12, R14
+	XORL	R13, R14
+	ADDL	R14, R9
+	ADDL	R11, R9
+	ADDL	$0xca62c1d6, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	20(SP), CX
+	XORL	(SP), CX
+	XORL	40(SP), CX
+	XORL	32(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 32(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0xca62c1d6, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	24(SP), CX
+	XORL	4(SP), CX
+	XORL	44(SP), CX
+	XORL	36(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 36(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0xca62c1d6, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	MOVL	28(SP), CX
+	XORL	8(SP), CX
+	XORL	48(SP), CX
+	XORL	40(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 40(SP)
+	MOVL	R13, R12
+	ROLL	$0x5, R12
+	MOVL	R11, R14
+	XORL	R9, R14
+	XORL	R10, R14
+	ADDL	R14, R12
+	ADDL	R8, R12
+	ADDL	$0xca62c1d6, R12
+	ADDL	CX, R12
+	ROLL	$0x1e, R11
+	MOVL	32(SP), CX
+	XORL	12(SP), CX
+	XORL	52(SP), CX
+	XORL	44(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 44(SP)
+	MOVL	R12, R8
+	ROLL	$0x5, R8
+	MOVL	R13, R14
+	XORL	R11, R14
+	XORL	R9, R14
+	ADDL	R14, R8
+	ADDL	R10, R8
+	ADDL	$0xca62c1d6, R8
+	ADDL	CX, R8
+	ROLL	$0x1e, R13
+	MOVL	36(SP), CX
+	XORL	16(SP), CX
+	XORL	56(SP), CX
+	XORL	48(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 48(SP)
+	MOVL	R8, R10
+	ROLL	$0x5, R10
+	MOVL	R12, R14
+	XORL	R13, R14
+	XORL	R11, R14
+	ADDL	R14, R10
+	ADDL	R9, R10
+	ADDL	$0xca62c1d6, R10
+	ADDL	CX, R10
+	ROLL	$0x1e, R12
+	MOVL	40(SP), CX
+	XORL	20(SP), CX
+	XORL	60(SP), CX
+	XORL	52(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 52(SP)
+	MOVL	R10, R9
+	ROLL	$0x5, R9
+	MOVL	R8, R14
+	XORL	R12, R14
+	XORL	R13, R14
+	ADDL	R14, R9
+	ADDL	R11, R9
+	ADDL	$0xca62c1d6, R9
+	ADDL	CX, R9
+	ROLL	$0x1e, R8
+	MOVL	44(SP), CX
+	XORL	24(SP), CX
+	XORL	(SP), CX
+	XORL	56(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 56(SP)
+	MOVL	R9, R11
+	ROLL	$0x5, R11
+	MOVL	R10, R14
+	XORL	R8, R14
+	XORL	R12, R14
+	ADDL	R14, R11
+	ADDL	R13, R11
+	ADDL	$0xca62c1d6, R11
+	ADDL	CX, R11
+	ROLL	$0x1e, R10
+	MOVL	48(SP), CX
+	XORL	28(SP), CX
+	XORL	4(SP), CX
+	XORL	60(SP), CX
+	ROLL	$0x1, CX
+	MOVL	CX, 60(SP)
+	MOVL	R11, R13
+	ROLL	$0x5, R13
+	MOVL	R9, R14
+	XORL	R10, R14
+	XORL	R8, R14
+	ADDL	R14, R13
+	ADDL	R12, R13
+	ADDL	$0xca62c1d6, R13
+	ADDL	CX, R13
+	ROLL	$0x1e, R9
+	ADDL	R13, DX
+	ADDL	R11, BX
+	ADDL	R9, BP
+	ADDL	R10, SI
+	ADDL	R8, DI
+	MOVL	DX, (AX)
+	MOVL	BX, 4(AX)
+	MOVL	BP, 8(AX)
+	MOVL	SI, 12(AX)
+	MOVL	DI, 16(AX)
+	RET
diff --git a/examples/sha1/sha1_test.go b/examples/sha1/sha1_test.go
new file mode 100644
index 0000000..892762f
--- /dev/null
+++ b/examples/sha1/sha1_test.go
@@ -0,0 +1,26 @@
+package sha1
+
+import (
+	"log"
+	"reflect"
+	"testing"
+)
+
+//go:generate go run asm.go -out sha1.s -stubs stub.go
+
+func TestEmptyString(t *testing.T) {
+	h := [...]uint32{0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0}
+	m := make([]byte, 64)
+	m[0] = 0x80
+
+	block(&h, m)
+
+	expect := [...]uint32{0xda39a3ee, 0x5e6b4b0d, 0x3255bfef, 0x95601890, 0xafd80709}
+
+	for i := 0; i < 5; i++ {
+		log.Printf("h[%d] = %08x", i, h[i])
+	}
+	if !reflect.DeepEqual(expect, h) {
+		t.Fatal("incorrect hash")
+	}
+}
diff --git a/examples/sha1/stub.go b/examples/sha1/stub.go
new file mode 100644
index 0000000..f51c0ec
--- /dev/null
+++ b/examples/sha1/stub.go
@@ -0,0 +1,5 @@
+// Code generated by command: go run asm.go -out sha1.s -stubs stub.go. DO NOT EDIT.
+
+package sha1
+
+func block(h *[5]uint32, m []byte)
diff --git a/operand/types.go b/operand/types.go
index 4e012a8..e655af1 100644
--- a/operand/types.go
+++ b/operand/types.go
@@ -44,6 +44,19 @@ func NewParamAddr(name string, offset int) Mem {
 	}
 }
 
+func NewStackAddr(offset int) Mem {
+	return Mem{
+		Disp: offset,
+		Base: reg.StackPointer,
+	}
+}
+
+func (m Mem) Idx(idx int) Mem {
+	a := m
+	a.Disp += idx
+	return a
+}
+
 func (m Mem) Asm() string {
 	a := m.Symbol.String()
 	if m.Disp != 0 {