Michael McLoughlin
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69ee0e39cb
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parameter loading
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2018-12-08 20:14:51 -08:00 |
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Michael McLoughlin
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82b31fa0da
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wip: adding instruction inputs and outputs
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2018-12-02 17:57:12 -08:00 |
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Michael McLoughlin
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43575d8b61
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start at some basic passes
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2018-12-02 13:51:03 -08:00 |
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Michael McLoughlin
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bed7e7e2c2
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stub operand checks
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2018-11-26 10:13:04 -08:00 |
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Michael McLoughlin
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af02be06ba
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add skeleton for instruction constructors
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2018-11-25 21:50:46 -08:00 |
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Michael McLoughlin
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4dcfed6e16
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add instruction arities function
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2018-11-25 18:25:51 -08:00 |
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Michael McLoughlin
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09848512cc
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add -bootstrap option to avogen
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2018-11-25 17:11:24 -08:00 |
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Michael McLoughlin
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0694ebab9b
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ensure all stdlib opcodes are present
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2018-11-25 16:22:02 -08:00 |
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Michael McLoughlin
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6d3e3be578
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generate test to ensure code generation worked
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2018-11-24 17:53:17 -08:00 |
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Michael McLoughlin
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0edbdb064f
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supporting more instructions seen in stdlib
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2018-11-24 17:32:18 -08:00 |
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Michael McLoughlin
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a70227cbe3
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test for stdlib opcodes
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2018-11-24 14:55:51 -08:00 |
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Michael McLoughlin
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898d66c585
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test asmtest with instruction list
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2018-11-24 14:20:04 -08:00 |
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Michael McLoughlin
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bec73ca7a1
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basic instruction properties
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2018-11-24 14:08:55 -08:00 |
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Michael McLoughlin
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70dcf2b611
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generate the instruction table
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2018-11-24 13:47:30 -08:00 |
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Michael McLoughlin
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4571841ee5
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fix implicit operands
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2018-11-23 23:48:47 -08:00 |
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Michael McLoughlin
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4e059c258b
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import isa and implicit operands
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2018-11-23 17:14:18 -06:00 |
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Michael McLoughlin
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59e6af7d36
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wip
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2018-11-21 13:02:18 -06:00 |
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Michael McLoughlin
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cb259ce43b
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rm x86csv stuff
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2018-11-20 15:12:04 -06:00 |
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Michael McLoughlin
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7c2990754f
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wip
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2018-11-20 11:44:44 -06:00 |
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