Commit Graph

16 Commits

Author SHA1 Message Date
33208a2356 update 2026-03-06 20:14:02 +00:00
Michael McLoughlin
f40d602170 reg,pass: refactor allocation of aliased registers (#121)
Issue #100 demonstrated that register allocation for aliased registers is
fundamentally broken. The root of the issue is that currently accesses to the
same virtual register with different masks are treated as different registers.
This PR takes a different approach:

* Liveness analysis is masked: we now properly consider which parts of a register are live
* Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later

In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended).

Closes #100
2020-01-22 22:50:40 -08:00
Michael McLoughlin
475a241446 operand: include '+0' in named symbol references
Intended to address an asmdecl error.

  [amd64] Butterfly: use of unnamed argument 0(FP); offset 0 is x0+0(FP)

Updates #24
2019-01-13 12:00:57 -08:00
Michael McLoughlin
2e250a6f4c operand: doc for exported symbols (#9) 2019-01-04 21:38:23 -08:00
Michael McLoughlin
9243d299e6 first pass at DATA sections 2018-12-27 11:57:46 -08:00
Michael McLoughlin
abd300c0e9 operand: const types 2018-12-26 16:42:39 -08:00
Michael McLoughlin
f464082484 examples/sha1: single block 2018-12-21 00:30:59 -08:00
Michael McLoughlin
2189d38d1e examples: add sum example (its not pretty) 2018-12-11 23:02:50 -08:00
Michael McLoughlin
bbbf6399a1 gotypes: saving progress (temporarily broken tests) 2018-12-07 18:37:42 -08:00
Michael McLoughlin
676ec39c51 add Symbol type to operand 2018-12-06 17:26:33 -08:00
Michael McLoughlin
022cbb7792 pass: first attempt at register allocation 2018-12-05 00:05:57 -08:00
Michael McLoughlin
7d4e18f4f4 ast: {Input,Output}Registers() 2018-12-02 22:29:30 -08:00
Michael McLoughlin
59548ee9f6 rename some register types 2018-12-02 21:35:33 -08:00
Michael McLoughlin
43575d8b61 start at some basic passes 2018-12-02 13:51:03 -08:00
Michael McLoughlin
4395adacc8 x86: rel types and generated tests 2018-11-27 22:08:11 -08:00
Michael McLoughlin
3050882621 start to implement operand types and checks 2018-11-26 22:14:36 -08:00