Adds the "Vector Bit Manipulation Instructions 2" instruction set.
These new instructions are added via the `opcodesextra` mechanism #345, since
they're missing from the opcodes database.
Contributed by @vsivsi. Extracted from #349 with simplifications.
Specifically, as prompted by the `dupl` linter we extract some common forms
lists into a helper `forms.go` file.
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds the AVX-512 Bit Algorithms instruction set.
These new instructions are added via the `opcodesextra` mechanism #345, since
they're missing from the opcodes database.
Contributed by @vsivsi. Extracted from #234 with simplifications for AVX-512
form expansion.
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds the VPOPCNTDQ instruction set, providing packed population count for
double and quadword integers.
These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database. In this case the 512-bit non-AVX512VL forms are
added here as well as the opcodes database, but they're deduplicated later.
Contributed by @vsivsi. Extracted from #234 with simplifications for AVX-512
form expansion.
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds VEX and EVEX encoded versions of the `PCLMULQDQ` carry-less quadword
multiplication instruction.
These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database.
Contributed by @vsivsi. Extracted from #349 with minor tweaks.
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds "Vector Neural Network Instructions" instruction set.
These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database.
Contributed by @vsivsi. Extracted from #349 with some tweaks.
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds "Vector Advanced Encryption Standard" instruction set.
These are added via the `opcodesextra` mechanism #345, since they're missing
from the opcodes database.
Contributed by @vsivsi. Extracted from #349 with minor tweaks.
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
Adds support for the GFNI "Galois Field New Instructions" instruction set.
These instructions are not included in the Opcodes database, therefore they're
added using the "extras" mechanism introduced in #345.
For simplicity, the loading phase is updated slightly so that AVX-512 form
expansion rules are applied after extras are added to the list. This greatly
reduces the number of forms that have to be specified by hand.
Based on #343Fixes#335
Co-authored-by: Klaus Post <klauspost@gmail.com>
Supporting extra instructions not included in the Opcodes database is
currently a challenge. Short of migrating to an entirely different source
(such as #23), the options are either to patch the XML data file or to append
additional instructions at the loading phase.
An example of patching the XML was shown in the as-yet unlanded PR #234. This
shows the XML patching approach is unwieldy and requires more information than
we actually need (for example instruction form encodings).
In #335 we discussed the alternative of adding extra instructions during
loading. This has the advantage of using avo's simpler internal data
structure.
This PR prepares for using that approach by adding an `internal/opcodesextra`
package, intended to contain manually curated lists of extra instructions to
add to the instruction database during loading. At the moment, the only
instruction added here is the `MOVLQZX` instruction that's already handled
this way.
Updates #335#234#23
Introduces a docgen tool for templated documentation generation, and uses it
to generate the README.
At the moment this change makes minimal difference to generating it with
embedmd. The difference is that docgen opens up the possibility to generate
documentation with more elaborate templating. The specific use case currently
in mind is including an adopters list that's kept in sync with the third-party
packages file.
Updates #101
Extends avo to support most AVX-512 instruction sets.
The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.
Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.
AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:
1. Instruction constructors in the `x86` package moved to an optab-based
approach. This compiles substantially faster than the verbose code
generation we had before.
2. The most verbose code-generated tests are moved under build tags and
limited to a stress test mode. Stress test builds are run on
schedule but not in regular CI.
An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.
Updates #20#163#229
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
As part of fixing failing third-party tests, this PR significantly
rearchitects their specification and execution.
Third-party tests are now specified in a much more flexible format allowing
more customization on a per-package level. In addition, third-party tests are
now used to auto-generate a Github Actions workflow to perform the tests in
parallel. This not only gives faster feedback on PRs, but will also allow us
to more quickly narrow down on which packages are failing. An additional
workflow also confirms that local execution of third-party tests is consistent
with the Github Actions version. This workflow only runs when tests/thirdparty
itself is changed.
Currently `avo` uses `BP` as a standard general-purpose register. However, `BP` is used for the frame pointer and should be callee-save. Under some circumstances, the Go assembler will do this automatically, but not always. At the moment `avo` can produce code that clobbers the `BP` register. Since Go 1.16 this code will also fail a new `go vet` check.
This PR provides a (currently sub-optimal) fix for the issue. It introduces an `EnsureBasePointerCalleeSaved` pass which will check if the base pointer is written to by a function, and if so will artificially ensure that the function has a non-zero frame size. This will trigger the Go assembler to automatically save and restore the BP register.
In addition, we update the `asmdecl` tool to `asmvet`, which includes the `framepointer` vet check.
Updates #156
This makes it easier to debug avogen: when you emit invalid syntax, you can inspect the generated file to determine what went wrong, instead of having only gofmt's error to work with.
Adds a regression test based on klauspost/compress#186. This necessitated some related changes:
* Mark "RET" as a terminal instruction
* printer refactor to maintain compatibility with asmfmt
* Tweaks to other regression tests to ensure they are run correctly in CI
Updates #100#65#8
Before printing a comment, remove trailing whitespace. Generation would output `// ` for empty comments. So we trim the whitespace off the end before printing.
Adds support for a `CancellingInputs` instruction flag, to indicate cases like `XORQ R10, R10` where the instruction actually does not depend on the value of `R10` at all.
Closes#89
Previously aliases were stored in a map which was causing
non-deterministic code generation (see recent build failures). This diff
changes to a slice to avoid this problem.
Updates #50
The Go assembler merges MOVD/MOVQ instruction forms. The logic in the
avo instruction loader was discarding the MOVD forms. This diff should
merge them correctly.
Updates #50
