Michael McLoughlin
b3644ec7fc
pass: tweak ordering in liveness analysis
...
Previously we updated the set of live in registers before live out. This
was extremely inefficient, since on each pass through live in depends on
live out.
We also change to processing the instructions in reverse order, which is
more likely to be efficient, although we should replace this with
topological sort order soon.
2018-12-24 12:48:29 -08:00
Michael McLoughlin
c70c642ddb
attempt to make register allocation deterministic
2018-12-13 00:34:44 -08:00
Michael McLoughlin
93b53377ac
add fnv1a example
2018-12-13 00:18:44 -08:00
Michael McLoughlin
b89d211ff4
examples/complex: and bugfixes
2018-12-12 00:02:22 -08:00
Michael McLoughlin
c882e52510
printing: commit some refactors (probably broken)
2018-12-11 00:18:22 -08:00
Michael McLoughlin
20525e1437
get the basic add example working
2018-12-08 22:02:02 -08:00
Michael McLoughlin
fa18d7229f
address some lint
2018-12-05 00:27:42 -08:00
Michael McLoughlin
022cbb7792
pass: first attempt at register allocation
2018-12-05 00:05:57 -08:00
Michael McLoughlin
9376a230cf
refactor to use reg.Set
2018-12-03 22:39:43 -08:00
Michael McLoughlin
faafa00e40
pass: test for liveness
2018-12-03 20:40:43 -08:00
Michael McLoughlin
b52c67f3fb
pass: naive implementation of liveness
2018-12-02 23:59:29 -08:00
Michael McLoughlin
f18271ada5
add reg.Type
2018-12-02 15:15:00 -08:00
Michael McLoughlin
bc7d0fa410
pass: cfg tests
2018-12-02 13:51:03 -08:00
Michael McLoughlin
43575d8b61
start at some basic passes
2018-12-02 13:51:03 -08:00
