f40d602170
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
332 lines
7.8 KiB
Go
332 lines
7.8 KiB
Go
package reg
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// Register kinds.
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const (
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KindPseudo Kind = iota
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KindGP
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KindVector
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)
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// Declare register families.
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var (
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Pseudo = &Family{Kind: KindPseudo}
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GeneralPurpose = &Family{Kind: KindGP}
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Vector = &Family{Kind: KindVector}
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Families = []*Family{
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Pseudo,
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GeneralPurpose,
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Vector,
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}
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)
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var familiesByKind = map[Kind]*Family{}
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func init() {
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for _, f := range Families {
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familiesByKind[f.Kind] = f
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}
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}
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// FamilyOfKind returns the Family of registers of the given kind, or nil if not found.
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func FamilyOfKind(k Kind) *Family {
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return familiesByKind[k]
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}
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// Pseudo registers.
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var (
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FramePointer = Pseudo.define(S0, 0, "FP")
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ProgramCounter = Pseudo.define(S0, 0, "PC")
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StaticBase = Pseudo.define(S0, 0, "SB")
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StackPointer = Pseudo.define(S0, 0, "SP")
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)
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// GP provides additional methods for general purpose registers.
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type GP interface {
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As8() Register
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As8L() Register
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As8H() Register
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As16() Register
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As32() Register
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As64() Register
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}
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// GPPhysical is a general-purpose physical register.
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type GPPhysical interface {
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Physical
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GP
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}
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type gpp struct {
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Physical
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}
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func newgpp(r Physical) GPPhysical { return gpp{Physical: r} }
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func (p gpp) As8() Register { return newgpp(p.as(S8).(Physical)) }
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func (p gpp) As8L() Register { return newgpp(p.as(S8L).(Physical)) }
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func (p gpp) As8H() Register { return newgpp(p.as(S8H).(Physical)) }
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func (p gpp) As16() Register { return newgpp(p.as(S16).(Physical)) }
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func (p gpp) As32() Register { return newgpp(p.as(S32).(Physical)) }
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func (p gpp) As64() Register { return newgpp(p.as(S64).(Physical)) }
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// GPVirtual is a general-purpose virtual register.
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type GPVirtual interface {
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Virtual
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GP
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}
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type gpv struct {
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Virtual
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}
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func newgpv(v Virtual) GPVirtual { return gpv{Virtual: v} }
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func (v gpv) As8() Register { return newgpv(v.as(S8).(Virtual)) }
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func (v gpv) As8L() Register { return newgpv(v.as(S8L).(Virtual)) }
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func (v gpv) As8H() Register { return newgpv(v.as(S8H).(Virtual)) }
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func (v gpv) As16() Register { return newgpv(v.as(S16).(Virtual)) }
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func (v gpv) As32() Register { return newgpv(v.as(S32).(Virtual)) }
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func (v gpv) As64() Register { return newgpv(v.as(S64).(Virtual)) }
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func gp(s Spec, id Index, name string, flags ...Info) GPPhysical {
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r := newgpp(newregister(GeneralPurpose, s, id, name, flags...))
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GeneralPurpose.add(r)
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return r
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}
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// General purpose registers.
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var (
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// Low byte
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AL = gp(S8L, 0, "AL")
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CL = gp(S8L, 1, "CL")
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DL = gp(S8L, 2, "DL")
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BL = gp(S8L, 3, "BL")
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// High byte
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AH = gp(S8H, 0, "AH")
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CH = gp(S8H, 1, "CH")
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DH = gp(S8H, 2, "DH")
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BH = gp(S8H, 3, "BH")
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// 8-bit
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SPB = gp(S8, 4, "SP", Restricted)
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BPB = gp(S8, 5, "BP")
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SIB = gp(S8, 6, "SI")
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DIB = gp(S8, 7, "DI")
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R8B = gp(S8, 8, "R8")
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R9B = gp(S8, 9, "R9")
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R10B = gp(S8, 10, "R10")
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R11B = gp(S8, 11, "R11")
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R12B = gp(S8, 12, "R12")
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R13B = gp(S8, 13, "R13")
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R14B = gp(S8, 14, "R14")
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R15B = gp(S8, 15, "R15")
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// 16-bit
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AX = gp(S16, 0, "AX")
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CX = gp(S16, 1, "CX")
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DX = gp(S16, 2, "DX")
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BX = gp(S16, 3, "BX")
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SP = gp(S16, 4, "SP", Restricted)
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BP = gp(S16, 5, "BP")
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SI = gp(S16, 6, "SI")
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DI = gp(S16, 7, "DI")
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R8W = gp(S16, 8, "R8")
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R9W = gp(S16, 9, "R9")
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R10W = gp(S16, 10, "R10")
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R11W = gp(S16, 11, "R11")
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R12W = gp(S16, 12, "R12")
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R13W = gp(S16, 13, "R13")
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R14W = gp(S16, 14, "R14")
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R15W = gp(S16, 15, "R15")
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// 32-bit
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EAX = gp(S32, 0, "AX")
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ECX = gp(S32, 1, "CX")
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EDX = gp(S32, 2, "DX")
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EBX = gp(S32, 3, "BX")
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ESP = gp(S32, 4, "SP", Restricted)
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EBP = gp(S32, 5, "BP")
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ESI = gp(S32, 6, "SI")
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EDI = gp(S32, 7, "DI")
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R8L = gp(S32, 8, "R8")
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R9L = gp(S32, 9, "R9")
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R10L = gp(S32, 10, "R10")
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R11L = gp(S32, 11, "R11")
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R12L = gp(S32, 12, "R12")
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R13L = gp(S32, 13, "R13")
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R14L = gp(S32, 14, "R14")
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R15L = gp(S32, 15, "R15")
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// 64-bit
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RAX = gp(S64, 0, "AX")
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RCX = gp(S64, 1, "CX")
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RDX = gp(S64, 2, "DX")
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RBX = gp(S64, 3, "BX")
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RSP = gp(S64, 4, "SP", Restricted)
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RBP = gp(S64, 5, "BP")
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RSI = gp(S64, 6, "SI")
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RDI = gp(S64, 7, "DI")
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R8 = gp(S64, 8, "R8")
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R9 = gp(S64, 9, "R9")
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R10 = gp(S64, 10, "R10")
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R11 = gp(S64, 11, "R11")
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R12 = gp(S64, 12, "R12")
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R13 = gp(S64, 13, "R13")
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R14 = gp(S64, 14, "R14")
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R15 = gp(S64, 15, "R15")
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)
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// Vec provides methods for vector registers.
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type Vec interface {
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AsX() Register
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AsY() Register
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AsZ() Register
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}
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// VecPhysical is a physical vector register.
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type VecPhysical interface {
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Physical
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Vec
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}
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type vecp struct {
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Physical
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Vec
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}
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func newvecp(r Physical) VecPhysical { return vecp{Physical: r} }
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func (p vecp) AsX() Register { return newvecp(p.as(S128).(Physical)) }
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func (p vecp) AsY() Register { return newvecp(p.as(S256).(Physical)) }
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func (p vecp) AsZ() Register { return newvecp(p.as(S512).(Physical)) }
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// VecVirtual is a virtual vector register.
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type VecVirtual interface {
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Virtual
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Vec
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}
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type vecv struct {
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Virtual
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Vec
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}
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func newvecv(v Virtual) VecVirtual { return vecv{Virtual: v} }
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func (v vecv) AsX() Register { return newvecv(v.as(S128).(Virtual)) }
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func (v vecv) AsY() Register { return newvecv(v.as(S256).(Virtual)) }
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func (v vecv) AsZ() Register { return newvecv(v.as(S512).(Virtual)) }
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func vec(s Spec, id Index, name string, flags ...Info) VecPhysical {
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r := newvecp(newregister(Vector, s, id, name, flags...))
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Vector.add(r)
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return r
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}
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// Vector registers.
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var (
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// 128-bit
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X0 = vec(S128, 0, "X0")
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X1 = vec(S128, 1, "X1")
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X2 = vec(S128, 2, "X2")
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X3 = vec(S128, 3, "X3")
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X4 = vec(S128, 4, "X4")
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X5 = vec(S128, 5, "X5")
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X6 = vec(S128, 6, "X6")
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X7 = vec(S128, 7, "X7")
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X8 = vec(S128, 8, "X8")
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X9 = vec(S128, 9, "X9")
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X10 = vec(S128, 10, "X10")
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X11 = vec(S128, 11, "X11")
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X12 = vec(S128, 12, "X12")
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X13 = vec(S128, 13, "X13")
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X14 = vec(S128, 14, "X14")
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X15 = vec(S128, 15, "X15")
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X16 = vec(S128, 16, "X16")
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X17 = vec(S128, 17, "X17")
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X18 = vec(S128, 18, "X18")
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X19 = vec(S128, 19, "X19")
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X20 = vec(S128, 20, "X20")
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X21 = vec(S128, 21, "X21")
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X22 = vec(S128, 22, "X22")
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X23 = vec(S128, 23, "X23")
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X24 = vec(S128, 24, "X24")
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X25 = vec(S128, 25, "X25")
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X26 = vec(S128, 26, "X26")
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X27 = vec(S128, 27, "X27")
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X28 = vec(S128, 28, "X28")
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X29 = vec(S128, 29, "X29")
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X30 = vec(S128, 30, "X30")
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X31 = vec(S128, 31, "X31")
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// 256-bit
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Y0 = vec(S256, 0, "Y0")
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Y1 = vec(S256, 1, "Y1")
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Y2 = vec(S256, 2, "Y2")
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Y3 = vec(S256, 3, "Y3")
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Y4 = vec(S256, 4, "Y4")
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Y5 = vec(S256, 5, "Y5")
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Y6 = vec(S256, 6, "Y6")
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Y7 = vec(S256, 7, "Y7")
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Y8 = vec(S256, 8, "Y8")
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Y9 = vec(S256, 9, "Y9")
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Y10 = vec(S256, 10, "Y10")
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Y11 = vec(S256, 11, "Y11")
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Y12 = vec(S256, 12, "Y12")
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Y13 = vec(S256, 13, "Y13")
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Y14 = vec(S256, 14, "Y14")
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Y15 = vec(S256, 15, "Y15")
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Y16 = vec(S256, 16, "Y16")
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Y17 = vec(S256, 17, "Y17")
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Y18 = vec(S256, 18, "Y18")
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Y19 = vec(S256, 19, "Y19")
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Y20 = vec(S256, 20, "Y20")
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Y21 = vec(S256, 21, "Y21")
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Y22 = vec(S256, 22, "Y22")
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Y23 = vec(S256, 23, "Y23")
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Y24 = vec(S256, 24, "Y24")
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Y25 = vec(S256, 25, "Y25")
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Y26 = vec(S256, 26, "Y26")
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Y27 = vec(S256, 27, "Y27")
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Y28 = vec(S256, 28, "Y28")
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Y29 = vec(S256, 29, "Y29")
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Y30 = vec(S256, 30, "Y30")
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Y31 = vec(S256, 31, "Y31")
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// 512-bit
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Z0 = vec(S512, 0, "Z0")
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Z1 = vec(S512, 1, "Z1")
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Z2 = vec(S512, 2, "Z2")
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Z3 = vec(S512, 3, "Z3")
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Z4 = vec(S512, 4, "Z4")
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Z5 = vec(S512, 5, "Z5")
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Z6 = vec(S512, 6, "Z6")
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Z7 = vec(S512, 7, "Z7")
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Z8 = vec(S512, 8, "Z8")
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Z9 = vec(S512, 9, "Z9")
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Z10 = vec(S512, 10, "Z10")
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Z11 = vec(S512, 11, "Z11")
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Z12 = vec(S512, 12, "Z12")
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Z13 = vec(S512, 13, "Z13")
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Z14 = vec(S512, 14, "Z14")
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Z15 = vec(S512, 15, "Z15")
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Z16 = vec(S512, 16, "Z16")
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Z17 = vec(S512, 17, "Z17")
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Z18 = vec(S512, 18, "Z18")
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Z19 = vec(S512, 19, "Z19")
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Z20 = vec(S512, 20, "Z20")
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Z21 = vec(S512, 21, "Z21")
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Z22 = vec(S512, 22, "Z22")
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Z23 = vec(S512, 23, "Z23")
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Z24 = vec(S512, 24, "Z24")
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Z25 = vec(S512, 25, "Z25")
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Z26 = vec(S512, 26, "Z26")
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Z27 = vec(S512, 27, "Z27")
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Z28 = vec(S512, 28, "Z28")
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Z29 = vec(S512, 29, "Z29")
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Z30 = vec(S512, 30, "Z30")
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Z31 = vec(S512, 31, "Z31")
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)
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