b76e849b5c
Extends avo to support most AVX-512 instruction sets.
The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.
Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.
AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:
1. Instruction constructors in the `x86` package moved to an optab-based
approach. This compiles substantially faster than the verbose code
generation we had before.
2. The most verbose code-generated tests are moved under build tags and
limited to a stress test mode. Stress test builds are run on
schedule but not in regular CI.
An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.
Updates #20 #163 #229
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
133 lines
3.0 KiB
Go
133 lines
3.0 KiB
Go
//go:build ignore
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// +build ignore
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package main
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import (
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"math"
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. "github.com/mmcloughlin/avo/build"
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. "github.com/mmcloughlin/avo/operand"
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. "github.com/mmcloughlin/avo/reg"
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)
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func main() {
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// Define round constants data section.
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//
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// These may be computed as the integer part of abs(sin(i+1))*2^32.
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T := GLOBL("consts", RODATA|NOPTR)
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for i := 0; i < 64; i++ {
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k := uint32(math.Floor(math.Ldexp(math.Abs(math.Sin(float64(i+1))), 32)))
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DATA(4*i, U32(k))
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}
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// MD5 16-lane block function.
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TEXT("block", 0, "func(h *[4][16]uint32, base uintptr, offsets *[16]uint32, mask uint16)")
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Doc(
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"block MD5 hashes 16 messages into the running hash states h. Messages are",
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"at the given offsets from the base pointer. The 16-bit mask specifies",
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"which lanes are active: when bit i is not set loads will be disabled and",
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"the value of the resulting hash is undefined.",
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)
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h := Mem{Base: Load(Param("h"), GP64())}
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base := Mem{Base: Load(Param("base"), GP64())}
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offsetsptr := Mem{Base: Load(Param("offsets"), GP64())}
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mask := Load(Param("mask"), K())
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Comment("Load offsets.")
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offsets := ZMM()
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VMOVUPD(offsetsptr, offsets)
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Comment("Load initial hash.")
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hash := [4]Register{ZMM(), ZMM(), ZMM(), ZMM()}
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for i, r := range hash {
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VMOVUPD(h.Offset(64*i), r)
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}
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Comment("Initialize registers.")
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a, b, c, d := ZMM(), ZMM(), ZMM(), ZMM()
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for i, r := range []Register{a, b, c, d} {
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VMOVUPD(hash[i], r)
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}
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// Allocate message registers.
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m := make([]Register, 16)
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for i := range m {
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m[i] = ZMM()
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}
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// Generate round updates.
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//
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// Each 16-round block is parameterized based on the btiwise function,
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// message indexes and shift amounts. Constants B, C, D are helpers in
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// computing the logic table required by VPTERNLOGD.
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const (
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B = uint8(0b10101010)
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C = uint8(0b11001100)
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D = uint8(0b11110000)
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)
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quarter := []struct {
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F uint8 // ternary logic table
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i func(int) int // message index at round r
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s []int // shift amounts
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}{
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{
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F: (B & C) | (^B & D),
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i: func(r int) int { return r % 16 },
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s: []int{7, 12, 17, 22},
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},
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{
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F: (D & B) | (^D & C),
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i: func(r int) int { return (5*r + 1) % 16 },
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s: []int{5, 9, 14, 20},
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},
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{
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F: B ^ C ^ D,
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i: func(r int) int { return (3*r + 5) % 16 },
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s: []int{4, 11, 16, 23},
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},
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{
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F: C ^ (B | ^D),
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i: func(r int) int { return (7 * r) % 16 },
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s: []int{6, 10, 15, 21},
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},
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}
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for r := 0; r < 64; r++ {
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Commentf("Round %d.", r)
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q := quarter[r/16]
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// Load message words.
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if r < 16 {
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k := K()
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KMOVW(mask, k)
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VPGATHERDD(base.Offset(4*r).Idx(offsets, 1), k, m[r])
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}
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VPADDD(m[q.i(r)], a, a)
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VPADDD_BCST(T.Offset(4*r), a, a)
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f := ZMM()
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VMOVUPD(d, f)
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VPTERNLOGD(U8(q.F), b, c, f)
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VPADDD(f, a, a)
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VPROLD(U8(q.s[r%4]), a, a)
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VPADDD(b, a, a)
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a, b, c, d = d, a, b, c
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}
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Comment("Final add.")
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for i, r := range []Register{a, b, c, d} {
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VPADDD(r, hash[i], hash[i])
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}
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Comment("Store results back.")
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for i, r := range hash {
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VMOVUPD(r, h.Offset(64*i))
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}
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VZEROUPPER()
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RET()
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Generate()
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}
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