26042 lines
495 KiB
Go
26042 lines
495 KiB
Go
// Code generated by command: avogen -bootstrap -data ../data -output ztable.go godata. DO NOT EDIT.
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package inst
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var Instructions = []Instruction{
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{
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Opcode: "ADCB",
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Summary: "Add with Carry",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "al", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r8", Action: 0x1},
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{Type: "r8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m8", Action: 0x1},
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{Type: "r8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r8", Action: 0x1},
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{Type: "m8", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADCL",
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Summary: "Add with Carry",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "eax", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r32", Action: 0x1},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m32", Action: 0x1},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "m32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r32", Action: 0x1},
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{Type: "m32", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADCQ",
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Summary: "Add with Carry",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "rax", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r64", Action: 0x1},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m64", Action: 0x1},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "m64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r64", Action: 0x1},
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{Type: "m64", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADCW",
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Summary: "Add with Carry",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm16", Action: 0x0},
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{Type: "ax", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r16", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm16", Action: 0x0},
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{Type: "r16", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r16", Action: 0x1},
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{Type: "r16", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m16", Action: 0x1},
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{Type: "r16", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m16", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm16", Action: 0x0},
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{Type: "m16", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r16", Action: 0x1},
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{Type: "m16", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADCXL",
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Summary: "Unsigned Integer Addition of Two Operands with Carry Flag",
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Forms: []Form{
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{
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ISA: []string{"ADX"},
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Operands: []Operand{
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{Type: "r32", Action: 0x1},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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ISA: []string{"ADX"},
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Operands: []Operand{
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{Type: "m32", Action: 0x1},
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{Type: "r32", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADCXQ",
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Summary: "Unsigned Integer Addition of Two Operands with Carry Flag",
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Forms: []Form{
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{
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ISA: []string{"ADX"},
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Operands: []Operand{
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{Type: "r64", Action: 0x1},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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ISA: []string{"ADX"},
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Operands: []Operand{
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{Type: "m64", Action: 0x1},
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{Type: "r64", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDB",
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Summary: "Add",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "al", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r8", Action: 0x1},
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{Type: "r8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m8", Action: 0x1},
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{Type: "r8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m8", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r8", Action: 0x1},
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{Type: "m8", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDL",
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Summary: "Add",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "eax", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r32", Action: 0x1},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m32", Action: 0x1},
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{Type: "r32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "m32", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r32", Action: 0x1},
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{Type: "m32", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDPD",
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Summary: "Add Packed Double-Precision Floating-Point Values",
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Forms: []Form{
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{
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ISA: []string{"SSE2"},
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Operands: []Operand{
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{Type: "xmm", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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{
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ISA: []string{"SSE2"},
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Operands: []Operand{
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{Type: "m128", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDPS",
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Summary: "Add Packed Single-Precision Floating-Point Values",
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Forms: []Form{
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{
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ISA: []string{"SSE"},
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Operands: []Operand{
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{Type: "xmm", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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{
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ISA: []string{"SSE"},
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Operands: []Operand{
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{Type: "m128", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDQ",
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Summary: "Add",
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Forms: []Form{
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "rax", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r64", Action: 0x1},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "m64", Action: 0x1},
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{Type: "r64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm8", Action: 0x0},
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{Type: "m64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "imm32", Action: 0x0},
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{Type: "m64", Action: 0x3},
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},
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},
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{
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Operands: []Operand{
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{Type: "r64", Action: 0x1},
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{Type: "m64", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDSD",
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Summary: "Add Scalar Double-Precision Floating-Point Values",
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Forms: []Form{
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{
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ISA: []string{"SSE2"},
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Operands: []Operand{
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{Type: "xmm", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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{
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ISA: []string{"SSE2"},
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Operands: []Operand{
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{Type: "m64", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDSS",
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Summary: "Add Scalar Single-Precision Floating-Point Values",
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Forms: []Form{
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{
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ISA: []string{"SSE"},
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Operands: []Operand{
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{Type: "xmm", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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{
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ISA: []string{"SSE"},
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Operands: []Operand{
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{Type: "m32", Action: 0x1},
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{Type: "xmm", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDSUBPD",
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Summary: "Packed Double-FP Add/Subtract",
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Forms: []Form{
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{
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ISA: []string{"SSE3"},
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|
Operands: []Operand{
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{Type: "xmm", Action: 0x1},
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|
{Type: "xmm", Action: 0x3},
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|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
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{Type: "m128", Action: 0x1},
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|
{Type: "xmm", Action: 0x3},
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},
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},
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},
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},
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{
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Opcode: "ADDSUBPS",
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Summary: "Packed Single-FP Add/Subtract",
|
|
Forms: []Form{
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{
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ISA: []string{"SSE3"},
|
|
Operands: []Operand{
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{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
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},
|
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},
|
|
},
|
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},
|
|
{
|
|
Opcode: "ADDW",
|
|
Summary: "Add",
|
|
Forms: []Form{
|
|
{
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Operands: []Operand{
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{Type: "imm16", Action: 0x0},
|
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{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
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{Type: "r16", Action: 0x3},
|
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},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
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},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ADOXL",
|
|
Summary: "Unsigned Integer Addition of Two Operands with Overflow Flag",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"ADX"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"ADX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ADOXQ",
|
|
Summary: "Unsigned Integer Addition of Two Operands with Overflow Flag",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"ADX"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"ADX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "AESDEC",
|
|
Summary: "Perform One Round of an AES Decryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "AESDECLAST",
|
|
Summary: "Perform Last Round of an AES Decryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "AESENC",
|
|
Summary: "Perform One Round of an AES Encryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "AESENCLAST",
|
|
Summary: "Perform Last Round of an AES Encryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "AESIMC",
|
|
Summary: "Perform the AES InvMixColumn Transformation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "AESKEYGENASSIST",
|
|
Summary: "AES Round Key Generation Assist",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AES"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDB",
|
|
Summary: "Logical AND",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "al", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDL",
|
|
Summary: "Logical AND",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "eax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDNL",
|
|
Summary: "Logical AND NOT",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDNPD",
|
|
Summary: "Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDNPS",
|
|
Summary: "Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDNQ",
|
|
Summary: "Logical AND NOT",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDPD",
|
|
Summary: "Bitwise Logical AND of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDPS",
|
|
Summary: "Bitwise Logical AND of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDQ",
|
|
Summary: "Logical AND",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "rax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ANDW",
|
|
Summary: "Logical AND",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BEXTRL",
|
|
Summary: "Bit Field Extract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BEXTRQ",
|
|
Summary: "Bit Field Extract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLENDPD",
|
|
Summary: "Blend Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLENDPS",
|
|
Summary: " Blend Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLENDVPD",
|
|
Summary: " Variable Blend Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLENDVPS",
|
|
Summary: " Variable Blend Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLSIL",
|
|
Summary: "Isolate Lowest Set Bit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLSIQ",
|
|
Summary: "Isolate Lowest Set Bit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLSMSKL",
|
|
Summary: "Mask From Lowest Set Bit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLSMSKQ",
|
|
Summary: "Mask From Lowest Set Bit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLSRL",
|
|
Summary: "Reset Lowest Set Bit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BLSRQ",
|
|
Summary: "Reset Lowest Set Bit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSFL",
|
|
Summary: "Bit Scan Forward",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSFQ",
|
|
Summary: "Bit Scan Forward",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSFW",
|
|
Summary: "Bit Scan Forward",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSRL",
|
|
Summary: "Bit Scan Reverse",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSRQ",
|
|
Summary: "Bit Scan Reverse",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSRW",
|
|
Summary: "Bit Scan Reverse",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSWAPL",
|
|
Summary: "Byte Swap",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BSWAPQ",
|
|
Summary: "Byte Swap",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTCL",
|
|
Summary: "Bit Test and Complement",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTCQ",
|
|
Summary: "Bit Test and Complement",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTCW",
|
|
Summary: "Bit Test and Complement",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTL",
|
|
Summary: "Bit Test",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTQ",
|
|
Summary: "Bit Test",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTRL",
|
|
Summary: "Bit Test and Reset",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTRQ",
|
|
Summary: "Bit Test and Reset",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTRW",
|
|
Summary: "Bit Test and Reset",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTSL",
|
|
Summary: "Bit Test and Set",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTSQ",
|
|
Summary: "Bit Test and Set",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTSW",
|
|
Summary: "Bit Test and Set",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BTW",
|
|
Summary: "Bit Test",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BZHIL",
|
|
Summary: "Zero High Bits Starting with Specified Bit Position",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "BZHIQ",
|
|
Summary: "Zero High Bits Starting with Specified Bit Position",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CALL",
|
|
Summary: "Call Procedure",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CBW",
|
|
Summary: "Convert Byte to Word",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x2},
|
|
{Register: "al", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CDQ",
|
|
Summary: "Convert Doubleword to Quadword",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CDQE",
|
|
Summary: "Convert Doubleword to Quadword",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "rax", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CLC",
|
|
Summary: "Clear Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CLD",
|
|
Summary: "Clear Direction Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CLFLUSH",
|
|
Summary: "Flush Cache Line",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CLFLUSH"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CLFLUSHOPT",
|
|
Summary: "Flush Cache Line Optimized",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CLFLUSHOPT"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMC",
|
|
Summary: "Complement Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLCC",
|
|
Summary: "Move if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLCS",
|
|
Summary: "Move if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLEQ",
|
|
Summary: "Move if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLGE",
|
|
Summary: "Move if greater or equal (SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLGT",
|
|
Summary: "Move if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLHI",
|
|
Summary: "Move if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLLE",
|
|
Summary: "Move if less or equal (ZF == 1 or SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLLS",
|
|
Summary: "Move if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLLT",
|
|
Summary: "Move if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLMI",
|
|
Summary: "Move if sign (SF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLNE",
|
|
Summary: "Move if not equal (ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLOC",
|
|
Summary: "Move if not overflow (OF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLOS",
|
|
Summary: "Move if overflow (OF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLPC",
|
|
Summary: "Move if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLPL",
|
|
Summary: "Move if not sign (SF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVLPS",
|
|
Summary: "Move if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQCC",
|
|
Summary: "Move if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQCS",
|
|
Summary: "Move if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQEQ",
|
|
Summary: "Move if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQGE",
|
|
Summary: "Move if greater or equal (SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQGT",
|
|
Summary: "Move if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQHI",
|
|
Summary: "Move if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQLE",
|
|
Summary: "Move if less or equal (ZF == 1 or SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQLS",
|
|
Summary: "Move if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQLT",
|
|
Summary: "Move if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQMI",
|
|
Summary: "Move if sign (SF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQNE",
|
|
Summary: "Move if not equal (ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQOC",
|
|
Summary: "Move if not overflow (OF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQOS",
|
|
Summary: "Move if overflow (OF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQPC",
|
|
Summary: "Move if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQPL",
|
|
Summary: "Move if not sign (SF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVQPS",
|
|
Summary: "Move if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWCC",
|
|
Summary: "Move if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWCS",
|
|
Summary: "Move if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWEQ",
|
|
Summary: "Move if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWGE",
|
|
Summary: "Move if greater or equal (SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWGT",
|
|
Summary: "Move if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWHI",
|
|
Summary: "Move if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWLE",
|
|
Summary: "Move if less or equal (ZF == 1 or SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWLS",
|
|
Summary: "Move if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWLT",
|
|
Summary: "Move if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWMI",
|
|
Summary: "Move if sign (SF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWNE",
|
|
Summary: "Move if not equal (ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWOC",
|
|
Summary: "Move if not overflow (OF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWOS",
|
|
Summary: "Move if overflow (OF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWPC",
|
|
Summary: "Move if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWPL",
|
|
Summary: "Move if not sign (SF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMOVWPS",
|
|
Summary: "Move if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"CMOV"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPB",
|
|
Summary: "Compare Two Operands",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "al", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPL",
|
|
Summary: "Compare Two Operands",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "eax", Action: 0x1},
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPPD",
|
|
Summary: "Compare Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPPS",
|
|
Summary: "Compare Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPQ",
|
|
Summary: "Compare Two Operands",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rax", Action: 0x1},
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPSD",
|
|
Summary: "Compare Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPSS",
|
|
Summary: "Compare Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPW",
|
|
Summary: "Compare Two Operands",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "ax", Action: 0x1},
|
|
{Type: "imm16", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "imm16", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "imm16", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPXCHG16B",
|
|
Summary: "Compare and Exchange 16 Bytes",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rbx", Action: 0x1},
|
|
{Register: "rcx", Action: 0x1},
|
|
{Register: "rdx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPXCHG8B",
|
|
Summary: "Compare and Exchange 8 Bytes",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "ebx", Action: 0x1},
|
|
{Register: "ecx", Action: 0x1},
|
|
{Register: "edx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPXCHGB",
|
|
Summary: "Compare and Exchange",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPXCHGL",
|
|
Summary: "Compare and Exchange",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPXCHGQ",
|
|
Summary: "Compare and Exchange",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CMPXCHGW",
|
|
Summary: "Compare and Exchange",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "COMISD",
|
|
Summary: "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "COMISS",
|
|
Summary: "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CPUID",
|
|
Summary: "CPU Identification",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"CPUID"},
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "ebx", Action: 0x2},
|
|
{Register: "ecx", Action: 0x3},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CQO",
|
|
Summary: "Convert Quadword to Octaword",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x1},
|
|
{Register: "rdx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CRC32B",
|
|
Summary: "Accumulate CRC32 Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CRC32L",
|
|
Summary: "Accumulate CRC32 Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CRC32Q",
|
|
Summary: "Accumulate CRC32 Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CRC32W",
|
|
Summary: "Accumulate CRC32 Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTPD2PL",
|
|
Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTPD2PS",
|
|
Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTPL2PD",
|
|
Summary: "Convert Packed Dword Integers to Packed Double-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTPL2PS",
|
|
Summary: "Convert Packed Dword Integers to Packed Single-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTPS2PD",
|
|
Summary: "Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTPS2PL",
|
|
Summary: "Convert Packed Single-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSD2SL",
|
|
Summary: "Convert Scalar Double-Precision FP Value to Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSD2SS",
|
|
Summary: "Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSL2SD",
|
|
Summary: "Convert Dword Integer to Scalar Double-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSL2SS",
|
|
Summary: "Convert Dword Integer to Scalar Single-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSQ2SD",
|
|
Summary: "Convert Dword Integer to Scalar Double-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSQ2SS",
|
|
Summary: "Convert Dword Integer to Scalar Single-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSS2SD",
|
|
Summary: "Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTSS2SL",
|
|
Summary: "Convert Scalar Single-Precision FP Value to Dword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTTPD2PL",
|
|
Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTTPS2PL",
|
|
Summary: "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTTSD2SL",
|
|
Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTTSD2SQ",
|
|
Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CVTTSS2SL",
|
|
Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CWD",
|
|
Summary: "Convert Word to Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x1},
|
|
{Register: "dx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "CWDE",
|
|
Summary: "Convert Word to Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x1},
|
|
{Register: "eax", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DECB",
|
|
Summary: "Decrement by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DECL",
|
|
Summary: "Decrement by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DECQ",
|
|
Summary: "Decrement by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DECW",
|
|
Summary: "Decrement by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVB",
|
|
Summary: "Unsigned Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVL",
|
|
Summary: "Unsigned Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVPD",
|
|
Summary: "Divide Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVPS",
|
|
Summary: "Divide Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVQ",
|
|
Summary: "Unsigned Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVSD",
|
|
Summary: "Divide Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVSS",
|
|
Summary: "Divide Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DIVW",
|
|
Summary: "Unsigned Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DPPD",
|
|
Summary: "Dot Product of Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "DPPS",
|
|
Summary: "Dot Product of Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "EXTRACTPS",
|
|
Summary: "Extract Packed Single Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm2u", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm2u", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "HADDPD",
|
|
Summary: "Packed Double-FP Horizontal Add",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "HADDPS",
|
|
Summary: "Packed Single-FP Horizontal Add",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "HSUBPD",
|
|
Summary: "Packed Double-FP Horizontal Subtract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "HSUBPS",
|
|
Summary: "Packed Single-FP Horizontal Subtract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IDIVB",
|
|
Summary: "Signed Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IDIVL",
|
|
Summary: "Signed Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IDIVQ",
|
|
Summary: "Signed Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IDIVW",
|
|
Summary: "Signed Divide",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMUL3L",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMUL3Q",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMUL3W",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMULB",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x2},
|
|
{Register: "al", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x2},
|
|
{Register: "al", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMULL",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMULQ",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "IMULW",
|
|
Summary: "Signed Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "INCB",
|
|
Summary: "Increment by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "INCL",
|
|
Summary: "Increment by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "INCQ",
|
|
Summary: "Increment by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "INCW",
|
|
Summary: "Increment by 1",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "INSERTPS",
|
|
Summary: "Insert Packed Single Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "INT",
|
|
Summary: "Call to Interrupt Procedure",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "3", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JA",
|
|
AliasOf: "JHI",
|
|
Summary: "Jump if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JAE",
|
|
AliasOf: "JCC",
|
|
Summary: "Jump if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JB",
|
|
AliasOf: "JCS",
|
|
Summary: "Jump if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JBE",
|
|
AliasOf: "JLS",
|
|
Summary: "Jump if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JC",
|
|
AliasOf: "JCS",
|
|
Summary: "Jump if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JCC",
|
|
Summary: "Jump if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JCS",
|
|
Summary: "Jump if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JCXZL",
|
|
Summary: "Jump if ECX register is 0",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ecx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JCXZQ",
|
|
Summary: "Jump if RCX register is 0",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rcx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JE",
|
|
AliasOf: "JEQ",
|
|
Summary: "Jump if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JEQ",
|
|
Summary: "Jump if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JG",
|
|
AliasOf: "JGT",
|
|
Summary: "Jump if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JGE",
|
|
Summary: "Jump if greater or equal (SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JGT",
|
|
Summary: "Jump if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JHI",
|
|
Summary: "Jump if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JHS",
|
|
AliasOf: "JCC",
|
|
Summary: "Jump if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JL",
|
|
AliasOf: "JLT",
|
|
Summary: "Jump if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JLE",
|
|
Summary: "Jump if less or equal (ZF == 1 or SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JLO",
|
|
AliasOf: "JCS",
|
|
Summary: "Jump if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JLS",
|
|
Summary: "Jump if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JLT",
|
|
Summary: "Jump if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JMI",
|
|
Summary: "Jump if sign (SF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JMP",
|
|
Summary: "Jump Unconditionally",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNA",
|
|
AliasOf: "JLS",
|
|
Summary: "Jump if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNAE",
|
|
AliasOf: "JCS",
|
|
Summary: "Jump if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNB",
|
|
AliasOf: "JCC",
|
|
Summary: "Jump if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNBE",
|
|
AliasOf: "JHI",
|
|
Summary: "Jump if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNC",
|
|
AliasOf: "JCC",
|
|
Summary: "Jump if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNE",
|
|
Summary: "Jump if not equal (ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNG",
|
|
AliasOf: "JLE",
|
|
Summary: "Jump if less or equal (ZF == 1 or SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNGE",
|
|
AliasOf: "JLT",
|
|
Summary: "Jump if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNL",
|
|
AliasOf: "JGE",
|
|
Summary: "Jump if greater or equal (SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNLE",
|
|
AliasOf: "JGT",
|
|
Summary: "Jump if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNO",
|
|
AliasOf: "JOC",
|
|
Summary: "Jump if not overflow (OF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNP",
|
|
AliasOf: "JPC",
|
|
Summary: "Jump if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNS",
|
|
AliasOf: "JPL",
|
|
Summary: "Jump if not sign (SF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JNZ",
|
|
AliasOf: "JNE",
|
|
Summary: "Jump if not equal (ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JO",
|
|
AliasOf: "JOS",
|
|
Summary: "Jump if overflow (OF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JOC",
|
|
Summary: "Jump if not overflow (OF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JOS",
|
|
Summary: "Jump if overflow (OF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JP",
|
|
AliasOf: "JPS",
|
|
Summary: "Jump if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JPC",
|
|
Summary: "Jump if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JPE",
|
|
AliasOf: "JPS",
|
|
Summary: "Jump if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JPL",
|
|
Summary: "Jump if not sign (SF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JPO",
|
|
AliasOf: "JPC",
|
|
Summary: "Jump if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JPS",
|
|
Summary: "Jump if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JS",
|
|
AliasOf: "JMI",
|
|
Summary: "Jump if sign (SF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "JZ",
|
|
AliasOf: "JEQ",
|
|
Summary: "Jump if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rel32", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LDDQU",
|
|
Summary: "Load Unaligned Integer 128 Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LDMXCSR",
|
|
Summary: "Load MXCSR Register",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LEAL",
|
|
Summary: "Load Effective Address",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LEAQ",
|
|
Summary: "Load Effective Address",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LEAW",
|
|
Summary: "Load Effective Address",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LFENCE",
|
|
Summary: "Load Fence",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LZCNTL",
|
|
Summary: "Count the Number of Leading Zero Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"LZCNT"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"LZCNT"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LZCNTQ",
|
|
Summary: "Count the Number of Leading Zero Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"LZCNT"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"LZCNT"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "LZCNTW",
|
|
Summary: "Count the Number of Leading Zero Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"LZCNT"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"LZCNT"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MASKMOVDQU",
|
|
AliasOf: "MASKMOVOU",
|
|
Summary: "Store Selected Bytes of Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rdi", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MASKMOVOU",
|
|
Summary: "Store Selected Bytes of Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rdi", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MAXPD",
|
|
Summary: "Return Maximum Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MAXPS",
|
|
Summary: "Return Maximum Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MAXSD",
|
|
Summary: "Return Maximum Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MAXSS",
|
|
Summary: "Return Maximum Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MFENCE",
|
|
Summary: "Memory Fence",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MINPD",
|
|
Summary: "Return Minimum Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MINPS",
|
|
Summary: "Return Minimum Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MINSD",
|
|
Summary: "Return Minimum Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MINSS",
|
|
Summary: "Return Minimum Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MONITOR",
|
|
Summary: "Monitor a Linear Address Range",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MONITOR"},
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x1},
|
|
{Register: "ecx", Action: 0x1},
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVAPD",
|
|
Summary: "Move Aligned Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVAPS",
|
|
Summary: "Move Aligned Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVB",
|
|
Summary: "Move",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBELL",
|
|
Summary: "Move Data After Swapping Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MOVBE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"MOVBE"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBEQQ",
|
|
Summary: "Move Data After Swapping Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MOVBE"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"MOVBE"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBEWW",
|
|
Summary: "Move Data After Swapping Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MOVBE"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"MOVBE"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBLSX",
|
|
Summary: "Move with Sign-Extension",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBLZX",
|
|
Summary: "Move with Zero-Extend",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBQSX",
|
|
Summary: "Move with Sign-Extension",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBQZX",
|
|
Summary: "Move with Zero-Extend",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBWSX",
|
|
Summary: "Move with Sign-Extension",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVBWZX",
|
|
Summary: "Move with Zero-Extend",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVD",
|
|
AliasOf: "MOVQ",
|
|
Summary: "Move",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm64", Action: 0x0},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVDDUP",
|
|
Summary: "Move One Double-FP and Duplicate",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVDQ2Q",
|
|
AliasOf: "MOVQ",
|
|
Summary: "Move",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm64", Action: 0x0},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVHLPS",
|
|
Summary: "Move Packed Single-Precision Floating-Point Values High to Low",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVHPD",
|
|
Summary: "Move High Packed Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVHPS",
|
|
Summary: "Move High Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVL",
|
|
Summary: "Move",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVLHPS",
|
|
Summary: "Move Packed Single-Precision Floating-Point Values Low to High",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVLPD",
|
|
Summary: "Move Low Packed Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVLPS",
|
|
Summary: "Move Low Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVLQSX",
|
|
Summary: "Move Doubleword to Quadword with Sign-Extension",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVLQZX",
|
|
Summary: "Move with Zero-Extend",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVMSKPD",
|
|
Summary: "Extract Packed Double-Precision Floating-Point Sign Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVMSKPS",
|
|
Summary: "Extract Packed Single-Precision Floating-Point Sign Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTDQ",
|
|
AliasOf: "MOVNTO",
|
|
Summary: "Store Double Quadword Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTDQA",
|
|
Summary: "Load Double Quadword Non-Temporal Aligned Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTIL",
|
|
Summary: "Store Doubleword Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTIQ",
|
|
Summary: "Store Doubleword Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTO",
|
|
Summary: "Store Double Quadword Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTPD",
|
|
Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVNTPS",
|
|
Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVO",
|
|
Summary: "Move Aligned Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVOA",
|
|
AliasOf: "MOVO",
|
|
Summary: "Move Aligned Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVOU",
|
|
Summary: "Move Unaligned Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVQ",
|
|
Summary: "Move",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm64", Action: 0x0},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVSD",
|
|
Summary: "Move Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVSHDUP",
|
|
Summary: "Move Packed Single-FP High and Duplicate",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVSLDUP",
|
|
Summary: "Move Packed Single-FP Low and Duplicate",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVSS",
|
|
Summary: "Move Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVUPD",
|
|
Summary: "Move Unaligned Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVUPS",
|
|
Summary: "Move Unaligned Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVW",
|
|
Summary: "Move",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVWLSX",
|
|
Summary: "Move with Sign-Extension",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVWLZX",
|
|
Summary: "Move with Zero-Extend",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVWQSX",
|
|
Summary: "Move with Sign-Extension",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MOVWQZX",
|
|
Summary: "Move with Zero-Extend",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MPSADBW",
|
|
Summary: "Compute Multiple Packed Sums of Absolute Difference",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULB",
|
|
Summary: "Unsigned Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x2},
|
|
{Register: "al", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x2},
|
|
{Register: "al", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULL",
|
|
Summary: "Unsigned Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x3},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULPD",
|
|
Summary: "Multiply Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULPS",
|
|
Summary: "Multiply Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULQ",
|
|
Summary: "Unsigned Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rax", Action: 0x3},
|
|
{Register: "rdx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULSD",
|
|
Summary: "Multiply Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULSS",
|
|
Summary: "Multiply Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULW",
|
|
Summary: "Unsigned Multiply",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ax", Action: 0x3},
|
|
{Register: "dx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULXL",
|
|
Summary: "Unsigned Multiply Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MULXQ",
|
|
Summary: "Unsigned Multiply Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rdx", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rdx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "MWAIT",
|
|
Summary: "Monitor Wait",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MONITOR"},
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "ecx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NEGB",
|
|
Summary: "Two's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NEGL",
|
|
Summary: "Two's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NEGQ",
|
|
Summary: "Two's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NEGW",
|
|
Summary: "Two's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NOP",
|
|
Summary: "No Operation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NOTB",
|
|
Summary: "One's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NOTL",
|
|
Summary: "One's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NOTQ",
|
|
Summary: "One's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "NOTW",
|
|
Summary: "One's Complement Negation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ORB",
|
|
Summary: "Logical Inclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "al", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ORL",
|
|
Summary: "Logical Inclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "eax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ORPD",
|
|
Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ORPS",
|
|
Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ORQ",
|
|
Summary: "Logical Inclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "rax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ORW",
|
|
Summary: "Logical Inclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PABSB",
|
|
Summary: "Packed Absolute Value of Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PABSD",
|
|
Summary: "Packed Absolute Value of Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PABSW",
|
|
Summary: "Packed Absolute Value of Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PACKSSLW",
|
|
Summary: "Pack Doublewords into Words with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PACKSSWB",
|
|
Summary: "Pack Words into Bytes with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PACKUSDW",
|
|
Summary: "Pack Doublewords into Words with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PACKUSWB",
|
|
Summary: "Pack Words into Bytes with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDB",
|
|
Summary: "Add Packed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDD",
|
|
AliasOf: "PADDL",
|
|
Summary: "Add Packed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDL",
|
|
Summary: "Add Packed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDQ",
|
|
Summary: "Add Packed Quadword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDSB",
|
|
Summary: "Add Packed Signed Byte Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDSW",
|
|
Summary: "Add Packed Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDUSB",
|
|
Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDUSW",
|
|
Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PADDW",
|
|
Summary: "Add Packed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PALIGNR",
|
|
Summary: "Packed Align Right",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PAND",
|
|
Summary: "Packed Bitwise Logical AND",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PANDN",
|
|
Summary: "Packed Bitwise Logical AND NOT",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PAUSE",
|
|
Summary: "Spin Loop Hint",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PAVGB",
|
|
Summary: "Average Packed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PAVGW",
|
|
Summary: "Average Packed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PBLENDVB",
|
|
Summary: "Variable Blend Packed Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PBLENDW",
|
|
Summary: "Blend Packed Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCLMULQDQ",
|
|
Summary: "Carry-Less Quadword Multiplication",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"PCLMULQDQ"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"PCLMULQDQ"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPEQB",
|
|
Summary: "Compare Packed Byte Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPEQL",
|
|
Summary: "Compare Packed Doubleword Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPEQQ",
|
|
Summary: "Compare Packed Quadword Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPEQW",
|
|
Summary: "Compare Packed Word Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPESTRI",
|
|
Summary: "Packed Compare Explicit Length Strings, Return Index",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "ecx", Action: 0x2},
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "ecx", Action: 0x2},
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPESTRM",
|
|
Summary: "Packed Compare Explicit Length Strings, Return Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "edx", Action: 0x1},
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "edx", Action: 0x1},
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPGTB",
|
|
Summary: "Compare Packed Signed Byte Integers for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPGTL",
|
|
Summary: "Compare Packed Signed Doubleword Integers for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPGTQ",
|
|
Summary: "Compare Packed Data for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPGTW",
|
|
Summary: "Compare Packed Signed Word Integers for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPISTRI",
|
|
Summary: "Packed Compare Implicit Length Strings, Return Index",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ecx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ecx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PCMPISTRM",
|
|
Summary: "Packed Compare Implicit Length Strings, Return Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PDEPL",
|
|
Summary: "Parallel Bits Deposit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PDEPQ",
|
|
Summary: "Parallel Bits Deposit",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PEXTL",
|
|
Summary: "Parallel Bits Extract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PEXTQ",
|
|
Summary: "Parallel Bits Extract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PEXTRB",
|
|
Summary: "Extract Byte",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PEXTRD",
|
|
Summary: "Extract Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PEXTRQ",
|
|
Summary: "Extract Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PEXTRW",
|
|
Summary: "Extract Word",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHADDD",
|
|
Summary: "Packed Horizontal Add Doubleword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHADDSW",
|
|
Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHADDW",
|
|
Summary: "Packed Horizontal Add Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHMINPOSUW",
|
|
Summary: "Packed Horizontal Minimum of Unsigned Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHSUBD",
|
|
Summary: "Packed Horizontal Subtract Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHSUBSW",
|
|
Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PHSUBW",
|
|
Summary: "Packed Horizontal Subtract Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PINSRB",
|
|
Summary: "Insert Byte",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PINSRD",
|
|
Summary: "Insert Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PINSRQ",
|
|
Summary: "Insert Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PINSRW",
|
|
Summary: "Insert Word",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMADDUBSW",
|
|
Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMADDWL",
|
|
Summary: "Multiply and Add Packed Signed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMAXSB",
|
|
Summary: "Maximum of Packed Signed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMAXSD",
|
|
Summary: "Maximum of Packed Signed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMAXSW",
|
|
Summary: "Maximum of Packed Signed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMAXUB",
|
|
Summary: "Maximum of Packed Unsigned Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMAXUD",
|
|
Summary: "Maximum of Packed Unsigned Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMAXUW",
|
|
Summary: "Maximum of Packed Unsigned Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMINSB",
|
|
Summary: "Minimum of Packed Signed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMINSD",
|
|
Summary: "Minimum of Packed Signed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMINSW",
|
|
Summary: "Minimum of Packed Signed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMINUB",
|
|
Summary: "Minimum of Packed Unsigned Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMINUD",
|
|
Summary: "Minimum of Packed Unsigned Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMINUW",
|
|
Summary: "Minimum of Packed Unsigned Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVMSKB",
|
|
Summary: "Move Byte Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVSXBD",
|
|
Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVSXBQ",
|
|
Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVSXBW",
|
|
Summary: "Move Packed Byte Integers to Word Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVSXDQ",
|
|
Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVSXWD",
|
|
Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVSXWQ",
|
|
Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVZXBD",
|
|
Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVZXBQ",
|
|
Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVZXBW",
|
|
Summary: "Move Packed Byte Integers to Word Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVZXDQ",
|
|
Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVZXWD",
|
|
Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMOVZXWQ",
|
|
Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULDQ",
|
|
Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULHRSW",
|
|
Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULHUW",
|
|
Summary: "Multiply Packed Unsigned Word Integers and Store High Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULHW",
|
|
Summary: "Multiply Packed Signed Word Integers and Store High Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULLD",
|
|
Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULLW",
|
|
Summary: "Multiply Packed Signed Word Integers and Store Low Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PMULULQ",
|
|
Summary: "Multiply Packed Unsigned Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "POPCNTL",
|
|
Summary: "Count of Number of Bits Set to 1",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"POPCNT"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"POPCNT"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "POPCNTQ",
|
|
Summary: "Count of Number of Bits Set to 1",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"POPCNT"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"POPCNT"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "POPCNTW",
|
|
Summary: "Count of Number of Bits Set to 1",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"POPCNT"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"POPCNT"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "POPQ",
|
|
Summary: "Pop a Value from the Stack",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "POPW",
|
|
Summary: "Pop a Value from the Stack",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "POR",
|
|
Summary: "Packed Bitwise Logical OR",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PREFETCHNTA",
|
|
Summary: "Prefetch Data Into Caches using NTA Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MMX+"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PREFETCHT0",
|
|
Summary: "Prefetch Data Into Caches using T0 Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MMX+"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PREFETCHT1",
|
|
Summary: "Prefetch Data Into Caches using T1 Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MMX+"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PREFETCHT2",
|
|
Summary: "Prefetch Data Into Caches using T2 Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MMX+"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSADBW",
|
|
Summary: "Compute Sum of Absolute Differences",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSHUFB",
|
|
Summary: "Packed Shuffle Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSHUFD",
|
|
AliasOf: "PSHUFL",
|
|
Summary: "Shuffle Packed Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSHUFHW",
|
|
Summary: "Shuffle Packed High Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSHUFL",
|
|
Summary: "Shuffle Packed Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSHUFLW",
|
|
Summary: "Shuffle Packed Low Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSIGNB",
|
|
Summary: "Packed Sign of Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSIGND",
|
|
Summary: "Packed Sign of Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSIGNW",
|
|
Summary: "Packed Sign of Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSSE3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSLLDQ",
|
|
AliasOf: "PSLLO",
|
|
Summary: "Shift Packed Double Quadword Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSLLL",
|
|
Summary: "Shift Packed Doubleword Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSLLO",
|
|
Summary: "Shift Packed Double Quadword Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSLLQ",
|
|
Summary: "Shift Packed Quadword Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSLLW",
|
|
Summary: "Shift Packed Word Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRAL",
|
|
Summary: "Shift Packed Doubleword Data Right Arithmetic",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRAW",
|
|
Summary: "Shift Packed Word Data Right Arithmetic",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRLDQ",
|
|
AliasOf: "PSRLO",
|
|
Summary: "Shift Packed Double Quadword Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRLL",
|
|
Summary: "Shift Packed Doubleword Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRLO",
|
|
Summary: "Shift Packed Double Quadword Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRLQ",
|
|
Summary: "Shift Packed Quadword Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSRLW",
|
|
Summary: "Shift Packed Word Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBB",
|
|
Summary: "Subtract Packed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBL",
|
|
Summary: "Subtract Packed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBQ",
|
|
Summary: "Subtract Packed Quadword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBSB",
|
|
Summary: "Subtract Packed Signed Byte Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBSW",
|
|
Summary: "Subtract Packed Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBUSB",
|
|
Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBUSW",
|
|
Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PSUBW",
|
|
Summary: "Subtract Packed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PTEST",
|
|
Summary: "Packed Logical Compare",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKHBW",
|
|
Summary: "Unpack and Interleave High-Order Bytes into Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKHLQ",
|
|
Summary: "Unpack and Interleave High-Order Doublewords into Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKHQDQ",
|
|
Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKHWL",
|
|
Summary: "Unpack and Interleave High-Order Words into Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKLBW",
|
|
Summary: "Unpack and Interleave Low-Order Bytes into Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKLLQ",
|
|
Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKLQDQ",
|
|
Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUNPCKLWL",
|
|
Summary: "Unpack and Interleave Low-Order Words into Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUSHQ",
|
|
Summary: "Push Value Onto the Stack",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PUSHW",
|
|
Summary: "Push Value Onto the Stack",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "PXOR",
|
|
Summary: "Packed Bitwise Logical Exclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCLB",
|
|
Summary: "Rotate Left through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCLL",
|
|
Summary: "Rotate Left through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCLQ",
|
|
Summary: "Rotate Left through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCLW",
|
|
Summary: "Rotate Left through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCPPS",
|
|
Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCPSS",
|
|
Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCRB",
|
|
Summary: "Rotate Right through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCRL",
|
|
Summary: "Rotate Right through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCRQ",
|
|
Summary: "Rotate Right through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RCRW",
|
|
Summary: "Rotate Right through Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDRANDL",
|
|
Summary: "Read Random Number",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDRAND"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDRANDQ",
|
|
Summary: "Read Random Number",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDRAND"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDRANDW",
|
|
Summary: "Read Random Number",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDRAND"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDSEEDL",
|
|
Summary: "Read Random SEED",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDSEED"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDSEEDQ",
|
|
Summary: "Read Random SEED",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDSEED"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDSEEDW",
|
|
Summary: "Read Random SEED",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDSEED"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDTSC",
|
|
Summary: "Read Time-Stamp Counter",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDTSC"},
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x2},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RDTSCP",
|
|
Summary: "Read Time-Stamp Counter and Processor ID",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"RDTSCP"},
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x2},
|
|
{Register: "ecx", Action: 0x2},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RET",
|
|
Summary: "Return from Procedure",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RETFL",
|
|
Summary: "Return from Procedure",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RETFQ",
|
|
Summary: "Return from Procedure",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RETFW",
|
|
Summary: "Return from Procedure",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROLB",
|
|
Summary: "Rotate Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROLL",
|
|
Summary: "Rotate Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROLQ",
|
|
Summary: "Rotate Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROLW",
|
|
Summary: "Rotate Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RORB",
|
|
Summary: "Rotate Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RORL",
|
|
Summary: "Rotate Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RORQ",
|
|
Summary: "Rotate Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RORW",
|
|
Summary: "Rotate Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RORXL",
|
|
Summary: "Rotate Right Logical Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RORXQ",
|
|
Summary: "Rotate Right Logical Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROUNDPD",
|
|
Summary: "Round Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROUNDPS",
|
|
Summary: "Round Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROUNDSD",
|
|
Summary: "Round Scalar Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "ROUNDSS",
|
|
Summary: "Round Scalar Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE4.1"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RSQRTPS",
|
|
Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "RSQRTSS",
|
|
Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SALB",
|
|
Summary: "Arithmetic Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SALL",
|
|
Summary: "Arithmetic Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SALQ",
|
|
Summary: "Arithmetic Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SALW",
|
|
Summary: "Arithmetic Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SARB",
|
|
Summary: "Arithmetic Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SARL",
|
|
Summary: "Arithmetic Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SARQ",
|
|
Summary: "Arithmetic Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SARW",
|
|
Summary: "Arithmetic Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SARXL",
|
|
Summary: "Arithmetic Shift Right Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SARXQ",
|
|
Summary: "Arithmetic Shift Right Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SBBB",
|
|
Summary: "Subtract with Borrow",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "al", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SBBL",
|
|
Summary: "Subtract with Borrow",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "eax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SBBQ",
|
|
Summary: "Subtract with Borrow",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "rax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SBBW",
|
|
Summary: "Subtract with Borrow",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETCC",
|
|
Summary: "Set byte if above or equal (CF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETCS",
|
|
Summary: "Set byte if below (CF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETEQ",
|
|
Summary: "Set byte if equal (ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETGE",
|
|
Summary: "Set byte if greater or equal (SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETGT",
|
|
Summary: "Set byte if greater (ZF == 0 and SF == OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETHI",
|
|
Summary: "Set byte if above (CF == 0 and ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETLE",
|
|
Summary: "Set byte if less or equal (ZF == 1 or SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETLS",
|
|
Summary: "Set byte if below or equal (CF == 1 or ZF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETLT",
|
|
Summary: "Set byte if less (SF != OF)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETMI",
|
|
Summary: "Set byte if sign (SF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETNE",
|
|
Summary: "Set byte if not equal (ZF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETOC",
|
|
Summary: "Set byte if not overflow (OF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETOS",
|
|
Summary: "Set byte if overflow (OF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETPC",
|
|
Summary: "Set byte if not parity (PF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETPL",
|
|
Summary: "Set byte if not sign (SF == 0)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SETPS",
|
|
Summary: "Set byte if parity (PF == 1)",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SFENCE",
|
|
Summary: "Store Fence",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"MMX+"},
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA1MSG1",
|
|
Summary: "Perform an Intermediate Calculation for the Next Four SHA1 Message Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA1MSG2",
|
|
Summary: "Perform a Final Calculation for the Next Four SHA1 Message Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA1NEXTE",
|
|
Summary: "Calculate SHA1 State Variable E after Four Rounds",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA1RNDS4",
|
|
Summary: "Perform Four Rounds of SHA1 Operation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "imm2u", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "imm2u", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA256MSG1",
|
|
Summary: "Perform an Intermediate Calculation for the Next Four SHA256 Message Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA256MSG2",
|
|
Summary: "Perform a Final Calculation for the Next Four SHA256 Message Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHA256RNDS2",
|
|
Summary: "Perform Two Rounds of SHA256 Operation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SHA"},
|
|
Operands: []Operand{
|
|
{Type: "xmm0", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHLB",
|
|
Summary: "Logical Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHLL",
|
|
Summary: "Logical Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHLQ",
|
|
Summary: "Logical Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHLW",
|
|
Summary: "Logical Shift Left",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHLXL",
|
|
Summary: "Logical Shift Left Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHLXQ",
|
|
Summary: "Logical Shift Left Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHRB",
|
|
Summary: "Logical Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHRL",
|
|
Summary: "Logical Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHRQ",
|
|
Summary: "Logical Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHRW",
|
|
Summary: "Logical Shift Right",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "1", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "cl", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHRXL",
|
|
Summary: "Logical Shift Right Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHRXQ",
|
|
Summary: "Logical Shift Right Without Affecting Flags",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI2"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHUFPD",
|
|
Summary: "Shuffle Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SHUFPS",
|
|
Summary: "Shuffle Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SQRTPD",
|
|
Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SQRTPS",
|
|
Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SQRTSD",
|
|
Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SQRTSS",
|
|
Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "STC",
|
|
Summary: "Set Carry Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "STD",
|
|
Summary: "Set Direction Flag",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "STMXCSR",
|
|
Summary: "Store MXCSR Register State",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBB",
|
|
Summary: "Subtract",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "al", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBL",
|
|
Summary: "Subtract",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "eax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBPD",
|
|
Summary: "Subtract Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBPS",
|
|
Summary: "Subtract Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBQ",
|
|
Summary: "Subtract",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "rax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBSD",
|
|
Summary: "Subtract Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBSS",
|
|
Summary: "Subtract Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SUBW",
|
|
Summary: "Subtract",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "SYSCALL",
|
|
Summary: "Fast System Call",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "r11", Action: 0x2},
|
|
{Register: "rcx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TESTB",
|
|
Summary: "Logical Compare",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "al", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TESTL",
|
|
Summary: "Logical Compare",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "eax", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TESTQ",
|
|
Summary: "Logical Compare",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "rax", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TESTW",
|
|
Summary: "Logical Compare",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "ax", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TZCNTL",
|
|
Summary: "Count the Number of Trailing Zero Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TZCNTQ",
|
|
Summary: "Count the Number of Trailing Zero Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "TZCNTW",
|
|
Summary: "Count the Number of Trailing Zero Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"BMI"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UCOMISD",
|
|
Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UCOMISS",
|
|
Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UD2",
|
|
Summary: "Undefined Instruction",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UNPCKHPD",
|
|
Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UNPCKHPS",
|
|
Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UNPCKLPD",
|
|
Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "UNPCKLPS",
|
|
Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VADDPD",
|
|
Summary: "Add Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VADDPS",
|
|
Summary: "Add Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VADDSD",
|
|
Summary: "Add Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VADDSS",
|
|
Summary: "Add Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VADDSUBPD",
|
|
Summary: "Packed Double-FP Add/Subtract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VADDSUBPS",
|
|
Summary: "Packed Single-FP Add/Subtract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VAESDEC",
|
|
Summary: "Perform One Round of an AES Decryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VAESDECLAST",
|
|
Summary: "Perform Last Round of an AES Decryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VAESENC",
|
|
Summary: "Perform One Round of an AES Encryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VAESENCLAST",
|
|
Summary: "Perform Last Round of an AES Encryption Flow",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VAESIMC",
|
|
Summary: "Perform the AES InvMixColumn Transformation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VAESKEYGENASSIST",
|
|
Summary: "AES Round Key Generation Assist",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "AES"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VANDNPD",
|
|
Summary: "Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VANDNPS",
|
|
Summary: "Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VANDPD",
|
|
Summary: "Bitwise Logical AND of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VANDPS",
|
|
Summary: "Bitwise Logical AND of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBLENDPD",
|
|
Summary: "Blend Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBLENDPS",
|
|
Summary: " Blend Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBLENDVPD",
|
|
Summary: " Variable Blend Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBLENDVPS",
|
|
Summary: " Variable Blend Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBROADCASTF128",
|
|
Summary: "Broadcast 128 Bit of Floating-Point Data",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBROADCASTI128",
|
|
Summary: "Broadcast 128 Bits of Integer Data",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBROADCASTSD",
|
|
Summary: "Broadcast Double-Precision Floating-Point Element",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VBROADCASTSS",
|
|
Summary: "Broadcast Single-Precision Floating-Point Element",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCMPPD",
|
|
Summary: "Compare Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCMPPS",
|
|
Summary: "Compare Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCMPSD",
|
|
Summary: "Compare Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCMPSS",
|
|
Summary: "Compare Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCOMISD",
|
|
Summary: "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCOMISS",
|
|
Summary: "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTDQ2PD",
|
|
Summary: "Convert Packed Dword Integers to Packed Double-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTDQ2PS",
|
|
Summary: "Convert Packed Dword Integers to Packed Single-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPD2DQX",
|
|
Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPD2DQY",
|
|
Summary: "Convert Packed Double-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPD2PSX",
|
|
Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPD2PSY",
|
|
Summary: "Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPH2PS",
|
|
Summary: "Convert Half-Precision FP Values to Single-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPS2DQ",
|
|
Summary: "Convert Packed Single-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPS2PD",
|
|
Summary: "Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTPS2PH",
|
|
Summary: "Convert Single-Precision FP value to Half-Precision FP value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"F16C"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSD2SI",
|
|
Summary: "Convert Scalar Double-Precision FP Value to Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSD2SIQ",
|
|
Summary: "Convert Scalar Double-Precision FP Value to Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSD2SS",
|
|
Summary: "Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSI2SDL",
|
|
Summary: "Convert Dword Integer to Scalar Double-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSI2SDQ",
|
|
Summary: "Convert Dword Integer to Scalar Double-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSI2SSL",
|
|
Summary: "Convert Dword Integer to Scalar Single-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSI2SSQ",
|
|
Summary: "Convert Dword Integer to Scalar Single-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSS2SD",
|
|
Summary: "Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSS2SI",
|
|
Summary: "Convert Scalar Single-Precision FP Value to Dword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTSS2SIQ",
|
|
Summary: "Convert Scalar Single-Precision FP Value to Dword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTPD2DQX",
|
|
Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTPD2DQY",
|
|
Summary: "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTPS2DQ",
|
|
Summary: "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTSD2SI",
|
|
Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTSD2SIQ",
|
|
Summary: "Convert with Truncation Scalar Double-Precision FP Value to Signed Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTSS2SI",
|
|
Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VCVTTSS2SIQ",
|
|
Summary: "Convert with Truncation Scalar Single-Precision FP Value to Dword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VDIVPD",
|
|
Summary: "Divide Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VDIVPS",
|
|
Summary: "Divide Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VDIVSD",
|
|
Summary: "Divide Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VDIVSS",
|
|
Summary: "Divide Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VDPPD",
|
|
Summary: "Dot Product of Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VDPPS",
|
|
Summary: "Dot Product of Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VEXTRACTF128",
|
|
Summary: "Extract Packed Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VEXTRACTI128",
|
|
Summary: "Extract Packed Integer Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VEXTRACTPS",
|
|
Summary: "Extract Packed Single Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD132PD",
|
|
Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD132PS",
|
|
Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD132SD",
|
|
Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD132SS",
|
|
Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD213PD",
|
|
Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD213PS",
|
|
Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD213SD",
|
|
Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD213SS",
|
|
Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD231PD",
|
|
Summary: "Fused Multiply-Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD231PS",
|
|
Summary: "Fused Multiply-Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD231SD",
|
|
Summary: "Fused Multiply-Add of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADD231SS",
|
|
Summary: "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADDSUB132PD",
|
|
Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADDSUB132PS",
|
|
Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADDSUB213PD",
|
|
Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADDSUB213PS",
|
|
Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADDSUB231PD",
|
|
Summary: "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMADDSUB231PS",
|
|
Summary: "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB132PD",
|
|
Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB132PS",
|
|
Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB132SD",
|
|
Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB132SS",
|
|
Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB213PD",
|
|
Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB213PS",
|
|
Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB213SD",
|
|
Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB213SS",
|
|
Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB231PD",
|
|
Summary: "Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB231PS",
|
|
Summary: "Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB231SD",
|
|
Summary: "Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUB231SS",
|
|
Summary: "Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUBADD132PD",
|
|
Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUBADD132PS",
|
|
Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUBADD213PD",
|
|
Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUBADD213PS",
|
|
Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUBADD231PD",
|
|
Summary: "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFMSUBADD231PS",
|
|
Summary: "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD132PD",
|
|
Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD132PS",
|
|
Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD132SD",
|
|
Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD132SS",
|
|
Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD213PD",
|
|
Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD213PS",
|
|
Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD213SD",
|
|
Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD213SS",
|
|
Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD231PD",
|
|
Summary: "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD231PS",
|
|
Summary: "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD231SD",
|
|
Summary: "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMADD231SS",
|
|
Summary: "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB132PD",
|
|
Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB132PS",
|
|
Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB132SD",
|
|
Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB132SS",
|
|
Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB213PD",
|
|
Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB213PS",
|
|
Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB213SD",
|
|
Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB213SS",
|
|
Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB231PD",
|
|
Summary: "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB231PS",
|
|
Summary: "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB231SD",
|
|
Summary: "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VFNMSUB231SS",
|
|
Summary: "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"FMA3"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VGATHERDPD",
|
|
Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Doubleword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm32x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x3},
|
|
{Type: "vm32x", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VGATHERDPS",
|
|
Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Doubleword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm32x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x3},
|
|
{Type: "vm32y", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VGATHERQPD",
|
|
Summary: "Gather Packed Double-Precision Floating-Point Values Using Signed Quadword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm64x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x3},
|
|
{Type: "vm64y", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VGATHERQPS",
|
|
Summary: "Gather Packed Single-Precision Floating-Point Values Using Signed Quadword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm64x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm64y", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VHADDPD",
|
|
Summary: "Packed Double-FP Horizontal Add",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VHADDPS",
|
|
Summary: "Packed Single-FP Horizontal Add",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VHSUBPD",
|
|
Summary: "Packed Double-FP Horizontal Subtract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VHSUBPS",
|
|
Summary: "Packed Single-FP Horizontal Subtract",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VINSERTF128",
|
|
Summary: "Insert Packed Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VINSERTI128",
|
|
Summary: "Insert Packed Integer Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VINSERTPS",
|
|
Summary: "Insert Packed Single Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VLDDQU",
|
|
Summary: "Load Unaligned Integer 128 Bits",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VLDMXCSR",
|
|
Summary: "Load MXCSR Register",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMASKMOVDQU",
|
|
Summary: "Store Selected Bytes of Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "rdi", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMASKMOVPD",
|
|
Summary: "Conditional Move Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMASKMOVPS",
|
|
Summary: "Conditional Move Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMAXPD",
|
|
Summary: "Return Maximum Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMAXPS",
|
|
Summary: "Return Maximum Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMAXSD",
|
|
Summary: "Return Maximum Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMAXSS",
|
|
Summary: "Return Maximum Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMINPD",
|
|
Summary: "Return Minimum Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMINPS",
|
|
Summary: "Return Minimum Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMINSD",
|
|
Summary: "Return Minimum Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMINSS",
|
|
Summary: "Return Minimum Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVAPD",
|
|
Summary: "Move Aligned Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVAPS",
|
|
Summary: "Move Aligned Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVD",
|
|
Summary: "Move Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVDDUP",
|
|
Summary: "Move One Double-FP and Duplicate",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVDQA",
|
|
Summary: "Move Aligned Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVDQU",
|
|
Summary: "Move Unaligned Double Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVHLPS",
|
|
Summary: "Move Packed Single-Precision Floating-Point Values High to Low",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVHPD",
|
|
Summary: "Move High Packed Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVHPS",
|
|
Summary: "Move High Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVLHPS",
|
|
Summary: "Move Packed Single-Precision Floating-Point Values Low to High",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVLPD",
|
|
Summary: "Move Low Packed Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVLPS",
|
|
Summary: "Move Low Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVMSKPD",
|
|
Summary: "Extract Packed Double-Precision Floating-Point Sign Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVMSKPS",
|
|
Summary: "Extract Packed Single-Precision Floating-Point Sign Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVNTDQ",
|
|
Summary: "Store Double Quadword Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVNTDQA",
|
|
Summary: "Load Double Quadword Non-Temporal Aligned Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVNTPD",
|
|
Summary: "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVNTPS",
|
|
Summary: "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVQ",
|
|
Summary: "Move Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVSD",
|
|
Summary: "Move Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVSHDUP",
|
|
Summary: "Move Packed Single-FP High and Duplicate",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVSLDUP",
|
|
Summary: "Move Packed Single-FP Low and Duplicate",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVSS",
|
|
Summary: "Move Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVUPD",
|
|
Summary: "Move Unaligned Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMOVUPS",
|
|
Summary: "Move Unaligned Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMPSADBW",
|
|
Summary: "Compute Multiple Packed Sums of Absolute Difference",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMULPD",
|
|
Summary: "Multiply Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMULPS",
|
|
Summary: "Multiply Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMULSD",
|
|
Summary: "Multiply Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VMULSS",
|
|
Summary: "Multiply Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VORPD",
|
|
Summary: "Bitwise Logical OR of Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VORPS",
|
|
Summary: "Bitwise Logical OR of Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPABSB",
|
|
Summary: "Packed Absolute Value of Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPABSD",
|
|
Summary: "Packed Absolute Value of Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPABSW",
|
|
Summary: "Packed Absolute Value of Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPACKSSDW",
|
|
Summary: "Pack Doublewords into Words with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPACKSSWB",
|
|
Summary: "Pack Words into Bytes with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPACKUSDW",
|
|
Summary: "Pack Doublewords into Words with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPACKUSWB",
|
|
Summary: "Pack Words into Bytes with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDB",
|
|
Summary: "Add Packed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDD",
|
|
Summary: "Add Packed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDQ",
|
|
Summary: "Add Packed Quadword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDSB",
|
|
Summary: "Add Packed Signed Byte Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDSW",
|
|
Summary: "Add Packed Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDUSB",
|
|
Summary: "Add Packed Unsigned Byte Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDUSW",
|
|
Summary: "Add Packed Unsigned Word Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPADDW",
|
|
Summary: "Add Packed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPALIGNR",
|
|
Summary: "Packed Align Right",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPAND",
|
|
Summary: "Packed Bitwise Logical AND",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPANDN",
|
|
Summary: "Packed Bitwise Logical AND NOT",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPAVGB",
|
|
Summary: "Average Packed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPAVGW",
|
|
Summary: "Average Packed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBLENDD",
|
|
Summary: "Blend Packed Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBLENDVB",
|
|
Summary: "Variable Blend Packed Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBLENDW",
|
|
Summary: "Blend Packed Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBROADCASTB",
|
|
Summary: "Broadcast Byte Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBROADCASTD",
|
|
Summary: "Broadcast Doubleword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBROADCASTQ",
|
|
Summary: "Broadcast Quadword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPBROADCASTW",
|
|
Summary: "Broadcast Word Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCLMULQDQ",
|
|
Summary: "Carry-Less Quadword Multiplication",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX", "PCLMULQDQ"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX", "PCLMULQDQ"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPEQB",
|
|
Summary: "Compare Packed Byte Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPEQD",
|
|
Summary: "Compare Packed Doubleword Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPEQQ",
|
|
Summary: "Compare Packed Quadword Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPEQW",
|
|
Summary: "Compare Packed Word Data for Equality",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPESTRI",
|
|
Summary: "Packed Compare Explicit Length Strings, Return Index",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "ecx", Action: 0x2},
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "ecx", Action: 0x2},
|
|
{Register: "edx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPESTRM",
|
|
Summary: "Packed Compare Explicit Length Strings, Return Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "edx", Action: 0x1},
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x1},
|
|
{Register: "edx", Action: 0x1},
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPGTB",
|
|
Summary: "Compare Packed Signed Byte Integers for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPGTD",
|
|
Summary: "Compare Packed Signed Doubleword Integers for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPGTQ",
|
|
Summary: "Compare Packed Data for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPGTW",
|
|
Summary: "Compare Packed Signed Word Integers for Greater Than",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPISTRI",
|
|
Summary: "Packed Compare Implicit Length Strings, Return Index",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ecx", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "ecx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPCMPISTRM",
|
|
Summary: "Packed Compare Implicit Length Strings, Return Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "xmm0", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERM2F128",
|
|
Summary: "Permute Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERM2I128",
|
|
Summary: "Permute 128-Bit Integer Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERMD",
|
|
Summary: "Permute Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERMILPD",
|
|
Summary: "Permute Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERMILPS",
|
|
Summary: "Permute Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERMPD",
|
|
Summary: "Permute Double-Precision Floating-Point Elements",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERMPS",
|
|
Summary: "Permute Single-Precision Floating-Point Elements",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPERMQ",
|
|
Summary: "Permute Quadword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPEXTRB",
|
|
Summary: "Extract Byte",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m8", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPEXTRD",
|
|
Summary: "Extract Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPEXTRQ",
|
|
Summary: "Extract Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r64", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m64", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPEXTRW",
|
|
Summary: "Extract Word",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m16", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPGATHERDD",
|
|
Summary: "Gather Packed Doubleword Values Using Signed Doubleword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm32x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x3},
|
|
{Type: "vm32y", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPGATHERDQ",
|
|
Summary: "Gather Packed Quadword Values Using Signed Doubleword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm32x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x3},
|
|
{Type: "vm32x", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPGATHERQD",
|
|
Summary: "Gather Packed Doubleword Values Using Signed Quadword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm64x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm64y", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPGATHERQQ",
|
|
Summary: "Gather Packed Quadword Values Using Signed Quadword Indices",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x3},
|
|
{Type: "vm64x", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x3},
|
|
{Type: "vm64y", Action: 0x1},
|
|
{Type: "ymm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHADDD",
|
|
Summary: "Packed Horizontal Add Doubleword Integer",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHADDSW",
|
|
Summary: "Packed Horizontal Add Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHADDW",
|
|
Summary: "Packed Horizontal Add Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHMINPOSUW",
|
|
Summary: "Packed Horizontal Minimum of Unsigned Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHSUBD",
|
|
Summary: "Packed Horizontal Subtract Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHSUBSW",
|
|
Summary: "Packed Horizontal Subtract Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPHSUBW",
|
|
Summary: "Packed Horizontal Subtract Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPINSRB",
|
|
Summary: "Insert Byte",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPINSRD",
|
|
Summary: "Insert Doubleword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPINSRQ",
|
|
Summary: "Insert Quadword",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPINSRW",
|
|
Summary: "Insert Word",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMADDUBSW",
|
|
Summary: "Multiply and Add Packed Signed and Unsigned Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMADDWD",
|
|
Summary: "Multiply and Add Packed Signed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMASKMOVD",
|
|
Summary: "Conditional Move Packed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMASKMOVQ",
|
|
Summary: "Conditional Move Packed Quadword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "m128", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "m256", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMAXSB",
|
|
Summary: "Maximum of Packed Signed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMAXSD",
|
|
Summary: "Maximum of Packed Signed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMAXSW",
|
|
Summary: "Maximum of Packed Signed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMAXUB",
|
|
Summary: "Maximum of Packed Unsigned Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMAXUD",
|
|
Summary: "Maximum of Packed Unsigned Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMAXUW",
|
|
Summary: "Maximum of Packed Unsigned Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMINSB",
|
|
Summary: "Minimum of Packed Signed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMINSD",
|
|
Summary: "Minimum of Packed Signed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMINSW",
|
|
Summary: "Minimum of Packed Signed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMINUB",
|
|
Summary: "Minimum of Packed Unsigned Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMINUD",
|
|
Summary: "Minimum of Packed Unsigned Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMINUW",
|
|
Summary: "Minimum of Packed Unsigned Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVMSKB",
|
|
Summary: "Move Byte Mask",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "r32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVSXBD",
|
|
Summary: "Move Packed Byte Integers to Doubleword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVSXBQ",
|
|
Summary: "Move Packed Byte Integers to Quadword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVSXBW",
|
|
Summary: "Move Packed Byte Integers to Word Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVSXDQ",
|
|
Summary: "Move Packed Doubleword Integers to Quadword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVSXWD",
|
|
Summary: "Move Packed Word Integers to Doubleword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVSXWQ",
|
|
Summary: "Move Packed Word Integers to Quadword Integers with Sign Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVZXBD",
|
|
Summary: "Move Packed Byte Integers to Doubleword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVZXBQ",
|
|
Summary: "Move Packed Byte Integers to Quadword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVZXBW",
|
|
Summary: "Move Packed Byte Integers to Word Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVZXDQ",
|
|
Summary: "Move Packed Doubleword Integers to Quadword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVZXWD",
|
|
Summary: "Move Packed Word Integers to Doubleword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMOVZXWQ",
|
|
Summary: "Move Packed Word Integers to Quadword Integers with Zero Extension",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULDQ",
|
|
Summary: "Multiply Packed Signed Doubleword Integers and Store Quadword Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULHRSW",
|
|
Summary: "Packed Multiply Signed Word Integers and Store High Result with Round and Scale",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULHUW",
|
|
Summary: "Multiply Packed Unsigned Word Integers and Store High Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULHW",
|
|
Summary: "Multiply Packed Signed Word Integers and Store High Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULLD",
|
|
Summary: "Multiply Packed Signed Doubleword Integers and Store Low Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULLW",
|
|
Summary: "Multiply Packed Signed Word Integers and Store Low Result",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPMULUDQ",
|
|
Summary: "Multiply Packed Unsigned Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPOR",
|
|
Summary: "Packed Bitwise Logical OR",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSADBW",
|
|
Summary: "Compute Sum of Absolute Differences",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSHUFB",
|
|
Summary: "Packed Shuffle Bytes",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSHUFD",
|
|
Summary: "Shuffle Packed Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSHUFHW",
|
|
Summary: "Shuffle Packed High Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSHUFLW",
|
|
Summary: "Shuffle Packed Low Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSIGNB",
|
|
Summary: "Packed Sign of Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSIGND",
|
|
Summary: "Packed Sign of Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSIGNW",
|
|
Summary: "Packed Sign of Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSLLD",
|
|
Summary: "Shift Packed Doubleword Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSLLDQ",
|
|
Summary: "Shift Packed Double Quadword Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSLLQ",
|
|
Summary: "Shift Packed Quadword Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSLLVD",
|
|
Summary: "Variable Shift Packed Doubleword Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSLLVQ",
|
|
Summary: "Variable Shift Packed Quadword Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSLLW",
|
|
Summary: "Shift Packed Word Data Left Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRAD",
|
|
Summary: "Shift Packed Doubleword Data Right Arithmetic",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRAVD",
|
|
Summary: "Variable Shift Packed Doubleword Data Right Arithmetic",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRAW",
|
|
Summary: "Shift Packed Word Data Right Arithmetic",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRLD",
|
|
Summary: "Shift Packed Doubleword Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRLDQ",
|
|
Summary: "Shift Packed Double Quadword Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRLQ",
|
|
Summary: "Shift Packed Quadword Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRLVD",
|
|
Summary: "Variable Shift Packed Doubleword Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRLVQ",
|
|
Summary: "Variable Shift Packed Quadword Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSRLW",
|
|
Summary: "Shift Packed Word Data Right Logical",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBB",
|
|
Summary: "Subtract Packed Byte Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBD",
|
|
Summary: "Subtract Packed Doubleword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBQ",
|
|
Summary: "Subtract Packed Quadword Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBSB",
|
|
Summary: "Subtract Packed Signed Byte Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBSW",
|
|
Summary: "Subtract Packed Signed Word Integers with Signed Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBUSB",
|
|
Summary: "Subtract Packed Unsigned Byte Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBUSW",
|
|
Summary: "Subtract Packed Unsigned Word Integers with Unsigned Saturation",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPSUBW",
|
|
Summary: "Subtract Packed Word Integers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPTEST",
|
|
Summary: "Packed Logical Compare",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKHBW",
|
|
Summary: "Unpack and Interleave High-Order Bytes into Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKHDQ",
|
|
Summary: "Unpack and Interleave High-Order Doublewords into Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKHQDQ",
|
|
Summary: "Unpack and Interleave High-Order Quadwords into Double Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKHWD",
|
|
Summary: "Unpack and Interleave High-Order Words into Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKLBW",
|
|
Summary: "Unpack and Interleave Low-Order Bytes into Words",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKLDQ",
|
|
Summary: "Unpack and Interleave Low-Order Doublewords into Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKLQDQ",
|
|
Summary: "Unpack and Interleave Low-Order Quadwords into Double Quadwords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPUNPCKLWD",
|
|
Summary: "Unpack and Interleave Low-Order Words into Doublewords",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VPXOR",
|
|
Summary: "Packed Bitwise Logical Exclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX2"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VRCPPS",
|
|
Summary: "Compute Approximate Reciprocals of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VRCPSS",
|
|
Summary: "Compute Approximate Reciprocal of Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VROUNDPD",
|
|
Summary: "Round Packed Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VROUNDPS",
|
|
Summary: "Round Packed Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VROUNDSD",
|
|
Summary: "Round Scalar Double Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VROUNDSS",
|
|
Summary: "Round Scalar Single Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VRSQRTPS",
|
|
Summary: "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VRSQRTSS",
|
|
Summary: "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSHUFPD",
|
|
Summary: "Shuffle Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSHUFPS",
|
|
Summary: "Shuffle Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSQRTPD",
|
|
Summary: "Compute Square Roots of Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSQRTPS",
|
|
Summary: "Compute Square Roots of Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSQRTSD",
|
|
Summary: "Compute Square Root of Scalar Double-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSQRTSS",
|
|
Summary: "Compute Square Root of Scalar Single-Precision Floating-Point Value",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSTMXCSR",
|
|
Summary: "Store MXCSR Register State",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSUBPD",
|
|
Summary: "Subtract Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSUBPS",
|
|
Summary: "Subtract Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSUBSD",
|
|
Summary: "Subtract Scalar Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VSUBSS",
|
|
Summary: "Subtract Scalar Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VTESTPD",
|
|
Summary: "Packed Double-Precision Floating-Point Bit Test",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VTESTPS",
|
|
Summary: "Packed Single-Precision Floating-Point Bit Test",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VUCOMISD",
|
|
Summary: "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VUCOMISS",
|
|
Summary: "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VUNPCKHPD",
|
|
Summary: "Unpack and Interleave High Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VUNPCKHPS",
|
|
Summary: "Unpack and Interleave High Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VUNPCKLPD",
|
|
Summary: "Unpack and Interleave Low Packed Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VUNPCKLPS",
|
|
Summary: "Unpack and Interleave Low Packed Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VXORPD",
|
|
Summary: "Bitwise Logical XOR for Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VXORPS",
|
|
Summary: "Bitwise Logical XOR for Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{
|
|
{Type: "m256", Action: 0x1},
|
|
{Type: "ymm", Action: 0x1},
|
|
{Type: "ymm", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VZEROALL",
|
|
Summary: "Zero All YMM Registers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "VZEROUPPER",
|
|
Summary: "Zero Upper Bits of YMM Registers",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"AVX"},
|
|
Operands: []Operand{},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XADDB",
|
|
Summary: "Exchange and Add",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XADDL",
|
|
Summary: "Exchange and Add",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XADDQ",
|
|
Summary: "Exchange and Add",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XADDW",
|
|
Summary: "Exchange and Add",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XCHGB",
|
|
Summary: "Exchange Register/Memory with Register",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x3},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x3},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XCHGL",
|
|
Summary: "Exchange Register/Memory with Register",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
{Type: "eax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "eax", Action: 0x3},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x3},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x3},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XCHGQ",
|
|
Summary: "Exchange Register/Memory with Register",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
{Type: "rax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "rax", Action: 0x3},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x3},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x3},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XCHGW",
|
|
Summary: "Exchange Register/Memory with Register",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "ax", Action: 0x3},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x3},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x3},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XGETBV",
|
|
Summary: "Get Value of Extended Control Register",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "eax", Action: 0x2},
|
|
{Register: "ecx", Action: 0x1},
|
|
{Register: "edx", Action: 0x2},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XLAT",
|
|
Summary: "Table Look-up Translation",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{},
|
|
ImplicitOperands: []ImplicitOperand{
|
|
{Register: "al", Action: 0x3},
|
|
{Register: "ebx", Action: 0x1},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XORB",
|
|
Summary: "Logical Exclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "al", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m8", Action: 0x1},
|
|
{Type: "r8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r8", Action: 0x1},
|
|
{Type: "m8", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XORL",
|
|
Summary: "Logical Exclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "eax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m32", Action: 0x1},
|
|
{Type: "r32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r32", Action: 0x1},
|
|
{Type: "m32", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XORPD",
|
|
Summary: "Bitwise Logical XOR for Double-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE2"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XORPS",
|
|
Summary: "Bitwise Logical XOR for Single-Precision Floating-Point Values",
|
|
Forms: []Form{
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "xmm", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
ISA: []string{"SSE"},
|
|
Operands: []Operand{
|
|
{Type: "m128", Action: 0x1},
|
|
{Type: "xmm", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XORQ",
|
|
Summary: "Logical Exclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "rax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m64", Action: 0x1},
|
|
{Type: "r64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm32", Action: 0x0},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r64", Action: 0x1},
|
|
{Type: "m64", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
{
|
|
Opcode: "XORW",
|
|
Summary: "Logical Exclusive OR",
|
|
Forms: []Form{
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "ax", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "m16", Action: 0x1},
|
|
{Type: "r16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm8", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "imm16", Action: 0x0},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
{
|
|
Operands: []Operand{
|
|
{Type: "r16", Action: 0x1},
|
|
{Type: "m16", Action: 0x3},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
}
|