f40d602170
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
140 lines
3.3 KiB
Go
140 lines
3.3 KiB
Go
package pass
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import (
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"errors"
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"github.com/mmcloughlin/avo/ir"
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"github.com/mmcloughlin/avo/operand"
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"github.com/mmcloughlin/avo/reg"
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)
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// ZeroExtend32BitOutputs applies the rule that "32-bit operands generate a
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// 32-bit result, zero-extended to a 64-bit result in the destination
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// general-purpose register" (Intel Software Developer’s Manual, Volume 1,
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// 3.4.1.1).
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func ZeroExtend32BitOutputs(i *ir.Instruction) error {
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for j, op := range i.Outputs {
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if !operand.IsR32(op) {
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continue
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}
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r, ok := op.(reg.GP)
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if !ok {
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panic("r32 operand should satisfy reg.GP")
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}
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i.Outputs[j] = r.As64()
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}
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return nil
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}
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// Liveness computes register liveness.
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func Liveness(fn *ir.Function) error {
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// Note this implementation is initially naive so as to be "obviously correct".
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// There are a well-known optimizations we can apply if necessary.
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is := fn.Instructions()
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// Process instructions in reverse: poor approximation to topological sort.
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// TODO(mbm): process instructions in topological sort order
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for l, r := 0, len(is)-1; l < r; l, r = l+1, r-1 {
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is[l], is[r] = is[r], is[l]
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}
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// Initialize.
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for _, i := range is {
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i.LiveIn = reg.NewMaskSetFromRegisters(i.InputRegisters())
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i.LiveOut = reg.NewEmptyMaskSet()
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}
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// Iterative dataflow analysis.
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for {
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changes := false
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for _, i := range is {
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// out[n] = UNION[s IN succ[n]] in[s]
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for _, s := range i.Succ {
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if s == nil {
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continue
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}
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changes = i.LiveOut.Update(s.LiveIn) || changes
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}
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// in[n] = use[n] UNION (out[n] - def[n])
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def := reg.NewMaskSetFromRegisters(i.OutputRegisters())
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changes = i.LiveIn.Update(i.LiveOut.Difference(def)) || changes
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}
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if !changes {
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break
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}
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}
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return nil
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}
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// AllocateRegisters performs register allocation.
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func AllocateRegisters(fn *ir.Function) error {
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// Populate allocators (one per kind).
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as := map[reg.Kind]*Allocator{}
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for _, i := range fn.Instructions() {
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for _, r := range i.Registers() {
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k := r.Kind()
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if _, found := as[k]; !found {
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a, err := NewAllocatorForKind(k)
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if err != nil {
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return err
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}
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as[k] = a
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}
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as[k].Add(r.ID())
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}
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}
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// Record register interferences.
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for _, i := range fn.Instructions() {
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for _, d := range i.OutputRegisters() {
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k := d.Kind()
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out := i.LiveOut.OfKind(k)
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out.DiscardRegister(d)
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as[k].AddInterferenceSet(d, out)
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}
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}
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// Execute register allocation.
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fn.Allocation = reg.NewEmptyAllocation()
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for _, a := range as {
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al, err := a.Allocate()
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if err != nil {
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return err
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}
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if err := fn.Allocation.Merge(al); err != nil {
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return err
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}
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}
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return nil
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}
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// BindRegisters applies the result of register allocation, replacing all virtual registers with their assigned physical registers.
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func BindRegisters(fn *ir.Function) error {
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for _, i := range fn.Instructions() {
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for idx := range i.Operands {
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i.Operands[idx] = operand.ApplyAllocation(i.Operands[idx], fn.Allocation)
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}
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}
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return nil
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}
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// VerifyAllocation performs sanity checks following register allocation.
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func VerifyAllocation(fn *ir.Function) error {
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// All registers should be physical.
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for _, i := range fn.Instructions() {
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for _, r := range i.Registers() {
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if reg.ToPhysical(r) == nil {
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return errors.New("non physical register found")
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}
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}
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}
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return nil
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}
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