f40d602170
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
46 lines
733 B
ArmAsm
46 lines
733 B
ArmAsm
// Code generated by command: go run asm.go -out gp8.s -stubs stub.go. DO NOT EDIT.
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#include "textflag.h"
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// func GP8() uint8
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TEXT ·GP8(SB), NOSPLIT, $0-1
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MOVB $0x01, AL
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MOVB $0x02, CL
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MOVB $0x03, DL
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MOVB $0x04, BL
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MOVB $0x05, BP
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MOVB $0x06, SI
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MOVB $0x07, DI
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MOVB $0x08, R8
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MOVB $0x09, R9
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MOVB $0x0a, R10
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MOVB $0x0b, R11
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MOVB $0x0c, R12
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MOVB $0x0d, R13
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MOVB $0x0e, R14
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MOVB $0x0f, R15
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MOVB $0x10, AH
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MOVB $0x11, CH
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MOVB $0x12, DH
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MOVB $0x13, BH
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ADDB CL, AL
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ADDB DL, AL
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ADDB BL, AL
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ADDB BP, AL
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ADDB SI, AL
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ADDB DI, AL
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ADDB R8, AL
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ADDB R9, AL
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ADDB R10, AL
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ADDB R11, AL
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ADDB R12, AL
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ADDB R13, AL
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ADDB R14, AL
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ADDB R15, AL
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ADDB AH, AL
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ADDB CH, AL
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ADDB DH, AL
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ADDB BH, AL
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MOVB AL, ret+0(FP)
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RET
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