f40d602170
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
49 lines
857 B
Go
49 lines
857 B
Go
// +build ignore
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package main
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import (
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"strconv"
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. "github.com/mmcloughlin/avo/build"
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. "github.com/mmcloughlin/avo/operand"
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. "github.com/mmcloughlin/avo/reg"
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)
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func main() {
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// n is the number of 8-bit registers to use.
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// 15 low-byte registers (excluding SP)
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// 4 high-byte registers AH,BH,CH,DH
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const n = 19
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TEXT("GP8", NOSPLIT, "func() uint8")
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Doc("GP8 returns the sum 1+2+...+" + strconv.Itoa(n) + " using " + strconv.Itoa(n) + " distinct 8-bit registers.")
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// Allocate registers and initialize.
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x := make([]Register, n)
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i := 0
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// Low byte registers.
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for ; i < 15; i++ {
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x[i] = GP8L()
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MOVB(U8(i+1), x[i])
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}
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// High byte registers.
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for ; i < n; i++ {
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x[i] = GP8H()
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MOVB(U8(i+1), x[i])
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}
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// Sum them up.
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for i := 1; i < n; i++ {
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ADDB(x[i], x[0])
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}
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// Return.
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Store(x[0], ReturnIndex(0))
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RET()
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Generate()
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}
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