Commit Graph

24 Commits

Author SHA1 Message Date
Michael McLoughlin
de9c629bcb operand: remove TODO about deleting Imm()
Starting to think this function could have its place.

Updates #18
2019-01-07 22:32:58 -08:00
Michael McLoughlin
5c67547d67 doc: add package-level doc comments (#9) 2019-01-05 17:23:56 -08:00
Michael McLoughlin
2e250a6f4c operand: doc for exported symbols (#9) 2019-01-04 21:38:23 -08:00
Michael McLoughlin
9fbb71b6db lint: enable golint
Enables golint and fixes function naming errors (operand checks
incorrectly cased).

Fixes #10
2018-12-31 11:20:59 -08:00
Michael McLoughlin
18cdf50d7c reg: support for register casting
Adds methods for referencing sub- or super-registers. For example, for
general purpose registers you can now reference As8(), As16(), ... and
for vector AsX(), AsY(), AsZ().

Closes #1
2018-12-30 18:40:45 -08:00
Michael McLoughlin
9243d299e6 first pass at DATA sections 2018-12-27 11:57:46 -08:00
Michael McLoughlin
abd300c0e9 operand: const types 2018-12-26 16:42:39 -08:00
Michael McLoughlin
f464082484 examples/sha1: single block 2018-12-21 00:30:59 -08:00
Michael McLoughlin
8282c9b17e fix operand check tests 2018-12-14 22:12:28 -08:00
Michael McLoughlin
93b53377ac add fnv1a example 2018-12-13 00:18:44 -08:00
Michael McLoughlin
2189d38d1e examples: add sum example (its not pretty) 2018-12-11 23:02:50 -08:00
Michael McLoughlin
5431f2edef support signatures and param load/stores 2018-12-08 21:16:03 -08:00
Michael McLoughlin
bbbf6399a1 gotypes: saving progress (temporarily broken tests) 2018-12-07 18:37:42 -08:00
Michael McLoughlin
676ec39c51 add Symbol type to operand 2018-12-06 17:26:33 -08:00
Michael McLoughlin
022cbb7792 pass: first attempt at register allocation 2018-12-05 00:05:57 -08:00
Michael McLoughlin
7d4e18f4f4 ast: {Input,Output}Registers() 2018-12-02 22:29:30 -08:00
Michael McLoughlin
59548ee9f6 rename some register types 2018-12-02 21:35:33 -08:00
Michael McLoughlin
f18271ada5 add reg.Type 2018-12-02 15:15:00 -08:00
Michael McLoughlin
43575d8b61 start at some basic passes 2018-12-02 13:51:03 -08:00
Michael McLoughlin
4395adacc8 x86: rel types and generated tests 2018-11-27 22:08:11 -08:00
Michael McLoughlin
3881907ec8 implement vm{32,64}{x,y} operand checks 2018-11-26 23:53:07 -08:00
Michael McLoughlin
0ec52ceaa8 add IsM* operand checks 2018-11-26 23:35:26 -08:00
Michael McLoughlin
3050882621 start to implement operand types and checks 2018-11-26 22:14:36 -08:00
Michael McLoughlin
bed7e7e2c2 stub operand checks 2018-11-26 10:13:04 -08:00