b985ff5775
Upgrade to Go 1.23. Upgrade also requires bumping `golangci-lint` to v1.62.2, and upgrading third-party test versions for some failing cases.
101 lines
3.0 KiB
Go
101 lines
3.0 KiB
Go
package x86
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import (
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"reflect"
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"testing"
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"github.com/mmcloughlin/avo/ir"
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"github.com/mmcloughlin/avo/operand"
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"github.com/mmcloughlin/avo/reg"
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)
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func TestCases(t *testing.T) {
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must := MustInstruction(t)
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m128 := operand.Mem{Base: reg.RAX}
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cases := []struct {
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Name string
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Instruction *ir.Instruction
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Expect *ir.Instruction
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}{
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// In the merge-masking case, the output register should also be an
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// input. This test confirms that Z3 appears in the input operands list.
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{
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Name: "avx512_masking_merging_input_registers",
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Instruction: must(VPADDD(reg.Z1, reg.Z2, reg.K1, reg.Z3)),
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Expect: &ir.Instruction{
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Opcode: "VPADDD",
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Operands: []operand.Op{reg.Z1, reg.Z2, reg.K1, reg.Z3},
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Inputs: []operand.Op{reg.Z1, reg.Z2, reg.K1, reg.Z3},
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Outputs: []operand.Op{reg.Z3},
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ISA: []string{"AVX512F"},
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},
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},
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// In the zeroing-masking case, the output register is not an input.
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// This test case is the same as above, but with the zeroing suffix. In
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// this case Z3 should not be an input.
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{
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Name: "avx512_masking_zeroing_input_registers",
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Instruction: must(VPADDD_Z(reg.Z1, reg.Z2, reg.K1, reg.Z3)),
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Expect: &ir.Instruction{
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Opcode: "VPADDD",
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Suffixes: []string{"Z"},
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Operands: []operand.Op{reg.Z1, reg.Z2, reg.K1, reg.Z3},
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Inputs: []operand.Op{reg.Z1, reg.Z2, reg.K1}, // not Z3
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Outputs: []operand.Op{reg.Z3},
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ISA: []string{"AVX512F"},
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},
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},
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// Many existing AVX instructions gained EVEX-encoded forms when AVX-512
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// was added. In a previous broken implementation, this led to multiple
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// forms of the same instruction in the database, both the VEX and EVEX
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// encoded versions. This causes the computed ISA list to be wrong,
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// since it can think AVX-512 is required when in fact the instruction
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// existed before. These test cases confirm the correct ISA is selected.
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{
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Name: "vex_evex_xmm_xmm_xmm",
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Instruction: must(VFMADD132PS(reg.X1, reg.X2, reg.X3)),
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Expect: &ir.Instruction{
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Opcode: "VFMADD132PS",
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Operands: []operand.Op{reg.X1, reg.X2, reg.X3},
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Inputs: []operand.Op{reg.X1, reg.X2, reg.X3},
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Outputs: []operand.Op{reg.X3},
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ISA: []string{"FMA3"}, // not AVX512F
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},
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},
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{
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Name: "vex_evex_m128_xmm_xmm",
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Instruction: must(VFMADD132PS(m128, reg.X2, reg.X3)),
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Expect: &ir.Instruction{
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Opcode: "VFMADD132PS",
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Operands: []operand.Op{m128, reg.X2, reg.X3},
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Inputs: []operand.Op{m128, reg.X2, reg.X3},
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Outputs: []operand.Op{reg.X3},
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ISA: []string{"FMA3"}, // not AVX512F
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},
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},
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}
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for _, c := range cases {
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t.Run(c.Name, func(t *testing.T) {
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if !reflect.DeepEqual(c.Instruction, c.Expect) {
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t.Logf(" got = %#v", c.Instruction)
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t.Logf("expect = %#v", c.Expect)
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t.FailNow()
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}
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})
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}
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}
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func MustInstruction(t *testing.T) func(*ir.Instruction, error) *ir.Instruction {
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t.Helper()
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return func(i *ir.Instruction, err error) *ir.Instruction {
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t.Helper()
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if err != nil {
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t.Fatal(err)
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}
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return i
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}
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}
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