b76e849b5c
Extends avo to support most AVX-512 instruction sets.
The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.
Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.
AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:
1. Instruction constructors in the `x86` package moved to an optab-based
approach. This compiles substantially faster than the verbose code
generation we had before.
2. The most verbose code-generated tests are moved under build tags and
limited to a stress test mode. Stress test builds are run on
schedule but not in regular CI.
An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.
Updates #20 #163 #229
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
80 lines
2.0 KiB
Go
80 lines
2.0 KiB
Go
//go:build ignore
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// +build ignore
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package main
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import (
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"strconv"
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. "github.com/mmcloughlin/avo/build"
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. "github.com/mmcloughlin/avo/operand"
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. "github.com/mmcloughlin/avo/reg"
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)
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// The goal of this test is to confirm correct liveness analysis of zeroing mode
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// when masking in AVX-512. In merge masking, some of the bits of the output
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// register will be preserved, so the register is live coming into the
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// instruction. Zeroing mode removes any input dependency.
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//
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// This synthetic test sets up a situation where we allocate multiple temporary
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// registers. Allocation is only feasible if the liveness pass correctly
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// identifies that they are not all live at once.
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func main() {
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const n = 32
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TEXT("Zeroing", NOSPLIT, "func(out *[8]uint64)")
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Doc("Zeroing computes the sum 1+2+...+" + strconv.Itoa(n) + " in 8 lanes of 512-bit register.")
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out := Load(Param("out"), GP64())
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Comment("Initialize sum.")
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s := ZMM()
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VPXORD(s, s, s)
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// Allocate registers for the terms of the sum. Write garbage to them.
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//
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// The point here is that under merge-masking, or an incorrect handling of
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// zeroing-masking, these registers would be live from this point. And there
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// would be too many of them so register allocation would fail.
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Comment("Initialize summand registers.")
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filler := GP64()
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MOVQ(U64(0x9e77d78aacb8cbcc), filler)
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z := make([]VecVirtual, n)
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for i := 0; i < n; i++ {
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z[i] = ZMM()
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VPBROADCASTQ(filler, z[i])
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}
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// Prepare a mask register set to all ones.
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Comment("Prepare mask register.")
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k := K()
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KXNORW(k, k, k)
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// Prepare an increment register set to 1 in each lane.
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Comment("Prepare constant registers.")
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one := GP64()
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MOVQ(U64(1), one)
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ones := ZMM()
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VPBROADCASTQ(one, ones)
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zero := ZMM()
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VPXORD(zero, zero, zero)
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last := zero
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for i := 0; i < n; i++ {
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Commentf("Summand %d.", i+1)
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VPADDD_Z(last, ones, k, z[i])
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VPADDD(s, z[i], s)
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last = z[i]
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}
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Comment("Write result to output pointer.")
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VMOVDQU64(s, Mem{Base: out})
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RET()
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Generate()
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}
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