b76e849b5c
Extends avo to support most AVX-512 instruction sets.
The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.
Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.
AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:
1. Instruction constructors in the `x86` package moved to an optab-based
approach. This compiles substantially faster than the verbose code
generation we had before.
2. The most verbose code-generated tests are moved under build tags and
limited to a stress test mode. Stress test builds are run on
schedule but not in regular CI.
An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.
Updates #20 #163 #229
Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
187 lines
3.2 KiB
ArmAsm
187 lines
3.2 KiB
ArmAsm
// Code generated by command: go run asm.go -out zeroing.s -stubs stub.go. DO NOT EDIT.
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#include "textflag.h"
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// func Zeroing(out *[8]uint64)
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// Requires: AVX512F
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TEXT ·Zeroing(SB), NOSPLIT, $0-8
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MOVQ out+0(FP), AX
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// Initialize sum.
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VPXORD Z0, Z0, Z0
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// Initialize summand registers.
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MOVQ $0x9e77d78aacb8cbcc, CX
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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VPBROADCASTQ CX, Z1
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// Prepare mask register.
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KXNORW K1, K1, K1
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// Prepare constant registers.
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MOVQ $0x0000000000000001, CX
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VPBROADCASTQ CX, Z2
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VPXORD Z3, Z3, Z3
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// Summand 1.
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VPADDD.Z Z3, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 2.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 3.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 4.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 5.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 6.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 7.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 8.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 9.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 10.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 11.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 12.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 13.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 14.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 15.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 16.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 17.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 18.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 19.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 20.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 21.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 22.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 23.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 24.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 25.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 26.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 27.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 28.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 29.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 30.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 31.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Summand 32.
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VPADDD.Z Z1, Z2, K1, Z1
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VPADDD Z0, Z1, Z0
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// Write result to output pointer.
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VMOVDQU64 Z0, (AX)
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RET
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