f40d602170
Issue #100 demonstrated that register allocation for aliased registers is fundamentally broken. The root of the issue is that currently accesses to the same virtual register with different masks are treated as different registers. This PR takes a different approach: * Liveness analysis is masked: we now properly consider which parts of a register are live * Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended). Closes #100
147 lines
3.1 KiB
ArmAsm
147 lines
3.1 KiB
ArmAsm
// Code generated by command: go run asm.go -out upper32.s -stubs stub.go. DO NOT EDIT.
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#include "textflag.h"
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// func Upper32() uint64
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TEXT ·Upper32(SB), NOSPLIT, $0-8
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// Initialize sum.
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XORQ AX, AX
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// Initialize registers.
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MOVQ $0x9e77d78aacb8cbcc, CX
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MOVQ $0x9e77d78aacb8cbcc, DX
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MOVQ $0x9e77d78aacb8cbcc, BX
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MOVQ $0x9e77d78aacb8cbcc, BP
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MOVQ $0x9e77d78aacb8cbcc, SI
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MOVQ $0x9e77d78aacb8cbcc, DI
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MOVQ $0x9e77d78aacb8cbcc, R8
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MOVQ $0x9e77d78aacb8cbcc, R9
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MOVQ $0x9e77d78aacb8cbcc, R10
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MOVQ $0x9e77d78aacb8cbcc, R11
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MOVQ $0x9e77d78aacb8cbcc, R12
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MOVQ $0x9e77d78aacb8cbcc, R13
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MOVQ $0x9e77d78aacb8cbcc, R14
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MOVQ $0x9e77d78aacb8cbcc, R15
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MOVQ $0x9e77d78aacb8cbcc, CX
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MOVQ $0x9e77d78aacb8cbcc, DX
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MOVQ $0x9e77d78aacb8cbcc, BX
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MOVQ $0x9e77d78aacb8cbcc, BP
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MOVQ $0x9e77d78aacb8cbcc, SI
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MOVQ $0x9e77d78aacb8cbcc, DI
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MOVQ $0x9e77d78aacb8cbcc, R8
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MOVQ $0x9e77d78aacb8cbcc, R9
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MOVQ $0x9e77d78aacb8cbcc, R10
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MOVQ $0x9e77d78aacb8cbcc, R11
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MOVQ $0x9e77d78aacb8cbcc, R12
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MOVQ $0x9e77d78aacb8cbcc, R13
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MOVQ $0x9e77d78aacb8cbcc, R14
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MOVQ $0x9e77d78aacb8cbcc, R15
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MOVQ $0x9e77d78aacb8cbcc, CX
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MOVQ $0x9e77d78aacb8cbcc, DX
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MOVQ $0x9e77d78aacb8cbcc, BX
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MOVQ $0x9e77d78aacb8cbcc, BP
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MOVQ $0x9e77d78aacb8cbcc, SI
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MOVQ $0x9e77d78aacb8cbcc, DI
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MOVQ $0x9e77d78aacb8cbcc, R8
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MOVQ $0x9e77d78aacb8cbcc, R9
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MOVQ $0x9e77d78aacb8cbcc, R10
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MOVQ $0x9e77d78aacb8cbcc, R11
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MOVQ $0x9e77d78aacb8cbcc, R12
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MOVQ $0x9e77d78aacb8cbcc, R13
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MOVQ $0x9e77d78aacb8cbcc, R14
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MOVQ $0x9e77d78aacb8cbcc, R15
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// Iteration 1.
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MOVL $0x00000001, CX
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MOVL $0x00000002, DX
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MOVL $0x00000003, BX
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MOVL $0x00000004, BP
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MOVL $0x00000005, SI
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MOVL $0x00000006, DI
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MOVL $0x00000007, R8
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MOVL $0x00000008, R9
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MOVL $0x00000009, R10
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MOVL $0x0000000a, R11
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MOVL $0x0000000b, R12
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MOVL $0x0000000c, R13
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MOVL $0x0000000d, R14
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MOVL $0x0000000e, R15
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ADDQ CX, AX
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ADDQ DX, AX
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ADDQ BX, AX
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ADDQ BP, AX
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ADDQ SI, AX
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ADDQ DI, AX
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ADDQ R8, AX
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ADDQ R9, AX
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ADDQ R10, AX
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ADDQ R11, AX
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ADDQ R12, AX
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ADDQ R13, AX
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ADDQ R14, AX
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ADDQ R15, AX
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// Iteration 2.
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MOVL $0x0000000f, CX
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MOVL $0x00000010, DX
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MOVL $0x00000011, BX
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MOVL $0x00000012, BP
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MOVL $0x00000013, SI
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MOVL $0x00000014, DI
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MOVL $0x00000015, R8
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MOVL $0x00000016, R9
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MOVL $0x00000017, R10
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MOVL $0x00000018, R11
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MOVL $0x00000019, R12
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MOVL $0x0000001a, R13
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MOVL $0x0000001b, R14
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MOVL $0x0000001c, R15
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ADDQ CX, AX
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ADDQ DX, AX
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ADDQ BX, AX
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ADDQ BP, AX
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ADDQ SI, AX
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ADDQ DI, AX
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ADDQ R8, AX
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ADDQ R9, AX
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ADDQ R10, AX
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ADDQ R11, AX
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ADDQ R12, AX
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ADDQ R13, AX
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ADDQ R14, AX
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ADDQ R15, AX
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// Iteration 3.
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MOVL $0x0000001d, CX
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MOVL $0x0000001e, DX
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MOVL $0x0000001f, BX
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MOVL $0x00000020, BP
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MOVL $0x00000021, SI
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MOVL $0x00000022, DI
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MOVL $0x00000023, R8
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MOVL $0x00000024, R9
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MOVL $0x00000025, R10
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MOVL $0x00000026, R11
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MOVL $0x00000027, R12
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MOVL $0x00000028, R13
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MOVL $0x00000029, R14
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MOVL $0x0000002a, R15
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ADDQ CX, AX
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ADDQ DX, AX
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ADDQ BX, AX
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ADDQ BP, AX
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ADDQ SI, AX
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ADDQ DI, AX
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ADDQ R8, AX
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ADDQ R9, AX
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ADDQ R10, AX
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ADDQ R11, AX
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ADDQ R12, AX
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ADDQ R13, AX
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ADDQ R14, AX
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ADDQ R15, AX
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// Store result and return.
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MOVQ AX, ret+0(FP)
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RET
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