Commit Graph

35 Commits

Author SHA1 Message Date
33208a2356 update 2026-03-06 20:14:02 +00:00
Michael McLoughlin
11e0a2138b all: enable use-any revive rule (#417)
Enable the `use-any` `revive` rule which requires replacing the empty
interface `interface{}` with `any`.
2024-01-07 13:16:59 -08:00
Michael McLoughlin
0d789c8353 operand: fix integer float data (#393)
Issue #387 pointed out that integer float data is printed incorrectly, such
that it is not parsed correctly by the Go assembler. Specifically, integer
values need the decimal point, otherwise they will be treated as integers. For
example, 1 must be represented as `$(1.)` or `$(1.0)` to be parsed correctly.

This PR fixes that problem and adds a regression test.  The root of the
problem was that the formatting verb `%#v` does not have the right behavior
for integers. We fix it by deferring to custom `String()` function for the
float operand types.

Fixes #387
Closes #388
2023-06-11 16:12:59 -07:00
Michael McLoughlin
34ac353c14 all: remove +build tags (#377)
Commit 759be3dad9 bumped our Go
requirement to 1.18 which allows us to drop support for old-style
`+build` tags. This change runs `go fix ./...` to remove them, and
updates some remaining code generators that produced `+build` lines.
2023-03-05 20:30:01 -08:00
Michael McLoughlin
b76e849b5c all: AVX-512 (#217)
Extends avo to support most AVX-512 instruction sets.

The instruction type is extended to support suffixes. The K family of opmask
registers is added to the register package, and the operand package is updated
to support the new operand types. Move instruction deduction in `Load` and
`Store` is extended to support KMOV* and VMOV* forms.

Internal code generation packages were overhauled. Instruction database loading
required various messy changes to account for the additional complexities of the
AVX-512 instruction sets. The internal/api package was added to introduce a
separation between instruction forms in the database, and the functions avo
provides to create them. This was required since with instruction suffixes there
is no longer a one-to-one mapping between instruction constructors and opcodes.

AVX-512 bloated generated source code size substantially, initially increasing
compilation and CI test times to an unacceptable level. Two changes were made to
address this:

1.  Instruction constructors in the `x86` package moved to an optab-based
    approach. This compiles substantially faster than the verbose code
    generation we had before.

2.  The most verbose code-generated tests are moved under build tags and
    limited to a stress test mode. Stress test builds are run on
    schedule but not in regular CI.

An example of AVX-512 accelerated 16-lane MD5 is provided to demonstrate and
test the new functionality.

Updates #20 #163 #229

Co-authored-by: Vaughn Iverson <vsivsi@yahoo.com>
2021-11-12 19:02:39 -08:00
Michael McLoughlin
9c70781236 all: go 1.17 (#197)
Bump CI Go versions to 1.16 and 1.17.
Update build tags with `go:build` equivalents.
Upgrade asmfmt tool for new `go:build` support.

Updates #183
2021-10-29 01:18:34 -07:00
Jeremy Larkin
4592e16ebb operand: allow signed immediates to be matched by IsIMMX (#182)
Many of the instruction functions correctly match the size of immediate values, but they only accept unsigned immediates. This PR fixes the operand check functions for intermediate types to also accept the signed variants.

Fixes #181
2021-04-16 15:12:12 -07:00
Michael McLoughlin
f40d602170 reg,pass: refactor allocation of aliased registers (#121)
Issue #100 demonstrated that register allocation for aliased registers is
fundamentally broken. The root of the issue is that currently accesses to the
same virtual register with different masks are treated as different registers.
This PR takes a different approach:

* Liveness analysis is masked: we now properly consider which parts of a register are live
* Register allocation produces a mapping from virtual to physical ID, and aliasing is applied later

In addition, a new pass ZeroExtend32BitOutputs accounts for the fact that 32-bit writes in 64-bit mode should actually be treated as 64-bit writes (the result is zero-extended).

Closes #100
2020-01-22 22:50:40 -08:00
Michael McLoughlin
1735441939 all: apply gofumpt (#79)
Apply @mvdan's opinionated gofumpt formatter across the codebase.
2019-04-13 22:53:13 -05:00
Michael McLoughlin
138eaf8dc3 reg: rename Bytes() to Size() (#74)
It was pointed out #73 that Bytes() is a poor name for the size of the register in bytes. In idiomatic Go you would probably expect a Bytes() method to return []byte.

This diff changes the Bytes() to Size(). As a result the Size type also needed to be renamed, and Width seemed a reasonable choice.

Fixes #73
2019-04-01 20:27:44 -07:00
Michael McLoughlin
475a241446 operand: include '+0' in named symbol references
Intended to address an asmdecl error.

  [amd64] Butterfly: use of unnamed argument 0(FP); offset 0 is x0+0(FP)

Updates #24
2019-01-13 12:00:57 -08:00
Michael McLoughlin
de9c629bcb operand: remove TODO about deleting Imm()
Starting to think this function could have its place.

Updates #18
2019-01-07 22:32:58 -08:00
Michael McLoughlin
5c67547d67 doc: add package-level doc comments (#9) 2019-01-05 17:23:56 -08:00
Michael McLoughlin
2e250a6f4c operand: doc for exported symbols (#9) 2019-01-04 21:38:23 -08:00
Michael McLoughlin
9fbb71b6db lint: enable golint
Enables golint and fixes function naming errors (operand checks
incorrectly cased).

Fixes #10
2018-12-31 11:20:59 -08:00
Michael McLoughlin
18cdf50d7c reg: support for register casting
Adds methods for referencing sub- or super-registers. For example, for
general purpose registers you can now reference As8(), As16(), ... and
for vector AsX(), AsY(), AsZ().

Closes #1
2018-12-30 18:40:45 -08:00
Michael McLoughlin
9243d299e6 first pass at DATA sections 2018-12-27 11:57:46 -08:00
Michael McLoughlin
abd300c0e9 operand: const types 2018-12-26 16:42:39 -08:00
Michael McLoughlin
f464082484 examples/sha1: single block 2018-12-21 00:30:59 -08:00
Michael McLoughlin
8282c9b17e fix operand check tests 2018-12-14 22:12:28 -08:00
Michael McLoughlin
93b53377ac add fnv1a example 2018-12-13 00:18:44 -08:00
Michael McLoughlin
2189d38d1e examples: add sum example (its not pretty) 2018-12-11 23:02:50 -08:00
Michael McLoughlin
5431f2edef support signatures and param load/stores 2018-12-08 21:16:03 -08:00
Michael McLoughlin
bbbf6399a1 gotypes: saving progress (temporarily broken tests) 2018-12-07 18:37:42 -08:00
Michael McLoughlin
676ec39c51 add Symbol type to operand 2018-12-06 17:26:33 -08:00
Michael McLoughlin
022cbb7792 pass: first attempt at register allocation 2018-12-05 00:05:57 -08:00
Michael McLoughlin
7d4e18f4f4 ast: {Input,Output}Registers() 2018-12-02 22:29:30 -08:00
Michael McLoughlin
59548ee9f6 rename some register types 2018-12-02 21:35:33 -08:00
Michael McLoughlin
f18271ada5 add reg.Type 2018-12-02 15:15:00 -08:00
Michael McLoughlin
43575d8b61 start at some basic passes 2018-12-02 13:51:03 -08:00
Michael McLoughlin
4395adacc8 x86: rel types and generated tests 2018-11-27 22:08:11 -08:00
Michael McLoughlin
3881907ec8 implement vm{32,64}{x,y} operand checks 2018-11-26 23:53:07 -08:00
Michael McLoughlin
0ec52ceaa8 add IsM* operand checks 2018-11-26 23:35:26 -08:00
Michael McLoughlin
3050882621 start to implement operand types and checks 2018-11-26 22:14:36 -08:00
Michael McLoughlin
bed7e7e2c2 stub operand checks 2018-11-26 10:13:04 -08:00